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sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 1 - product list ......................................................................................................................................................................... 3 description .......................................................................................................................................................................... 3 ordering information ........................................................................................................................................................... 3 features .............................................................................................................................................................................. 3 pin configuration ................................................................................................................................................................ 4 block diagram ..................................................................................................................................................................... 6 special function register (sfr) ........................................................................................................................................ 8 function description ......................................................................................................................................................... 14 1. general features ................................................................................................................................................. 14 1.1 embedded flash ......................................................................................................................................... 14 1.2 io pads ....................................................................................................................................................... 14 1.3 instruction timing selection ......................................................................................................................... 14 1.4 clock out selection ..................................................................................................................................... 15 1.5 reset ........................................................................................................................................................ 15 1.5.1 hardware reset function ................................................................................................................. 15 1.5.2 software reset function ................................................................................................................... 15 1.5.3 reset status ........................................................................................................................................ 16 1.5.4 tim e access key register (takey) .................................................................................................... 16 1.5.5 software reset register (swres) ..................................................................................................... 17 1.5.6 example of software reset .................................................................................................................. 17 1.6 clocks ......................................................................................................................................................... 17 2. instruction set ...................................................................................................................................................... 18 3. memory structure ................................................................................................................................................ 22 3.1 program memory ........................................................................................................................................ 22 3.2 data memory ............................................................................................................................................... 23 3.3 data memory - lower 128 byte (00h to 7fh) ............................................................................................... 23 3.4 data memory - higher 128 byte (80h to ffh) .............................................................................................. 23 3.5 data memory - expanded 1k bytes ( 0000h ~ 03ffh) ............................................................................... 23 4. cpu engine ......................................................................................................................................................... 24 4.1 accumulator ................................................................................................................................................ 24 4.2 b register ................................................................................................................................................... 24 4.3 program status word .................................................................................................................................. 25 4.4 stack pointer ............................................................................................................................................... 25 4.5 data pointer ................................................................................................................................................ 25 4.6 data pointer 1 ............................................................................................................................................. 26 4.7 clock control register .................................................................................................................................. 26 4.8 interface control register ............................................................................................................................. 27 4.9 pagesel (page select) ............................................................................................................................. 27 5. gpio .................................................................................................................................................................... 29 5.1 sfr setting method .................................................................................................................................... 29 5.2 software of writer setting method .............................................................................................................. 30 6. multiplication division unit .................................................................................................................................... 31 6.1 operating registers of the mdu .................................................................................................................. 31 6.2 operation of the mdu ................................................................................................................................. 32 6.2.1 first phase: loading the mdx registers. ............................................................................................ 32 6.2.2 second phase: executing calculation. ............................................................................................... 32 6.2.3 third phase: reading the result from the mdx registers. .................................................................. 33 6.3 normalizing ................................................................................................................................................. 33 6.4 shifting ........................................................................................................................................................ 33 7. timer 0 and timer 1 ............................................................................................................................................. 34 7.1 timer/counter mode control register (tmod) ............................................................................................ 34 7.2 timer/counter control register (tcon) ....................................................................................................... 35 7.3 enhance interrupt trigger sfr(enhit) ...................................................................................................... 36 7.4 peripheral frequency control register ......................................................................................................... 36 7.5 mode 0 (13 - bit counter/time r) .................................................................................................................... 37 7.6 mode 1 (16 - bit counter/timer) .................................................................................................................... 38
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 2 - 7.7 mode 2 (8 - bit auto - reload counter/timer) .................................................................................................. 38 7.8 mode 3 (timer 0 acts as two independent 8 bit timers / counters) ........................................................... 39 8. timer 2 and capture compare unit ..................................................................................................................... 40 8.1 timer 2 function ........................................................................................................................................... 43 8.1.1 timer mode ........................................................................................................................................ 43 8.1.2 event counter mode ........................................................................................................................... 43 8.1.3 gated timer mode ............................................................................................................................... 43 8.1.4 reload of timer 2 ............................................................................................................................... 44 8.2 compare function ........................................................................................................................................ 45 8.2.1 compare mode 0 ................................................................................................................................ 45 8.2.2 compare mode 1 ................................................................................................................................ 45 8.3 capture function .......................................................................................................................................... 47 8.3.1 capture mode 0 (by hardware) .......................................................................................................... 47 8.3.2 capture mode 1(by software) ............................................................................................................ 47 9. serial inte rface ..................................................................................................................................................... 48 9.1 serial interface ............................................................................................................................................ 49 9.1.1 mode 0 ................................................................................................................................................ 49 9.1.2 mode 1 ................................................................................................................................................ 50 9.1.3 mode 2 ................................................................................................................................................ 50 9.1.4 mode 3 ................................................................................................................................................ 50 9.2 multiprocessor communicatio n of serial interface ..................................................................................... 51 9.3 peripheral frequency control register ......................................................................................................... 51 9.4 baud rate generator .................................................................................................................................... 52 9.4.1 serial interface modes 1 and 3 ........................................................................................................... 52 10. watchdog timer .................................................................................................................................................... 53 11. interrupt ................................................................................................................................................................ 57 11.1 priority level structure .................................................................................................................................. 60 12. power management unit ..................................................................................................................................... 62 12.1 idle mode .................................................................................................................................................... 62 12.2 stop mode ................................................................................................................................................... 62 13. pulse width modulation (pwm) ........................................................................................................................... 63 14. iic fu nction ........................................................................................................................................................... 68 15. spi function - serial peripheral interface ........................................................................................................... 73 16. lvi & lvr ? low voltage interrupt and low voltage reset ................................................................................ 78 17. 10- bit analog - to - digital converter (adc) ............................................................................................................ 80 18. in - system programming (internal isp) ................................................................................................................ 84 18.1 isp service program .................................................................................................................................... 84 18.2 lock bit (n) ................................................................................................................................................. 84 18.3 program the isp service program .............................................................................................................. 85 18.4 initiate isp service program ....................................................................................................................... 85 18.5 isp register ? takey, ifcon, ispfah, ispfal, ispfd and ispfc ........................................................ 86 operating conditions ........................................................................................................................................................ 89 dc characteristics ............................................................................................................................................................ 89 lvi& lvr characteristics .................................................................................................................................................. 91
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 3 - product list sm39 r 16 a6 u2 4 , sm39 r 16 a6 u28 , sm39 r 16 a6 u32 , description the SM39R16A6 is a 1t (one machine cycle per clock) single - chip 8 - bit microcontroller. it has 16 k - byte embedded flash for program, and executes all asm51 instructio ns fully compati ble with mcs - 51 SM39R16A6 contains 1k+256 b on - chip ram, up to 30 gpios ( 32l package) , various serial interfaces and many peripheral functions as described below. it can be programmed via writers. its on - chip ice is convenient for users in verification dur ing development stage. the high performance of SM39R16A6 can achieve complicated manipulation within short time. about one third of the instructions are pure 1t, and the average speed is 8 times of traditional 8051, the fastest one among all the 1t 51 - s eries.its excellent emi and esd characteristics are advantageous for many different applications. ordering information SM39R16A6 ihhkl yww i: process identifier { u = 1.8v ~ 5.5v} hh: pin count k: package type postfix {as table below } l:pb free identifie r {no text is non - pb free ?p? is pb free} y : year ww : week postfix package s sop (300 mil) v lqfp features ? main flash rom 16kb , 128b/page ? working voltage 1.8v~5.5v ? high speed architecture of 1 clock/machine cycle runs up to 25mhz. ? 256 bytes s ram as standard 8052, plus 1 k bytes on- chip expandable s ram . ? dual 16 - bit data pointers (dptr0 & dptr1) . ? one serial peripheral inter faces in full duplex mode (uart ) . - synchronous mode, fixed baud rate. - 8 - bit uart mode, variable baud rate. - 9 - bit uart mode, fixed baud rate. - 9 - bit uart mode, variable baud rate. ? additional baud rate generator for serial port . ? three 16 - bit timer/counters. (timer 0, 1, 2) . ? programmable watchdog timer. ? one iic interface. (master/slave mode) . ? one spi interface. (master/slave mode) ? 4 - cha nnel 14 - bit pwm for motor control ? 4 - channel 16 - bit compare / capture / load functions . - c omparator out can be ccu input source internally. - n oise filter with ccu input with sample frequency select. ? isp/iap /icp functions. ? eeprom function. ? on - chip in - circuit e mulator (ice) functions with on - chip debugger (ocd). ? fast multiplication - division unit (mdu): 16*16, 32/16, 16/16, 32 - bit l/r shifting and 32 - bit normalization. ? lv i /lvr (lvr deglitch 500ns) . ? enhance user code protection. ? power management unit for idle and power down modes.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 4 - pin configurati on 24 pin sop 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 sm 39 r 16 a 6 u 24 sp yww ( 24 pin top view ) p 1 . 2 / adc 2 / t 2 / cc 1 p 1 . 3 / adc 3 / t 2 ex p 1 . 4 / adc 4 / ss / cc 3 p 0 . 4 / pwm 4 p 0 . 5 / pwm 5 p 0 . 6 / int 1 / pwm 6 p 0 . 7 / t 1 / pwm 7 reset / p 3 . 4 p 1 . 1 / adc 1 / txd / cc 0 oci _ s da / iic _ sda / trigadc / p 3 . 2 oci _ s cl / iic _ scl / p 3 . 3 vdd 14 13 11 12 t 0 / spi _ clk / adc 7 / p 1 . 7 p 1 . 0 / adc 0 / rxd xtal 1 / p 3 . 6 vss clkout / xtal 2 / p 3 . 5 p 1 . 5 / adc 5 / mosi p 1 . 6 / adc 6 / miso / int 0 cc 0 / p 2 . 0 cc 1 / p 2 . 1 cc 2 / p 2 . 2 cc 3 / p 2 . 3 p 2 . 6 syncmos 28 pin sop 1 2 3 4 5 6 7 8 9 10 27 26 25 24 23 22 21 20 19 18 15 16 17 28 12 14 11 sm 39r16a6u28sp yww (28 pin top view) p1.2/adc2/t2/cc1 p1.3/adc3/t2ex/cc2 p1.4/adc4/ss/cc3 p0.4/pwm4 p0.5/pwm5 p0.6/int1/pwm6 p0.7/t1/pwm7 reset/p3.4 p1.1/adc1/txd/cc0 oci_sda/iic_sda/trigadc/p3.2 oci_scl/iic_scl/p3.3 vdd p1.0/adc0/rxd xtal1/p3.6 vss clkout/xtal2/p3.5 p1.5/adc5/mosi p1.6/adc6/miso/int0 cc0/p2.0 cc1/p2.1 cc2/p2.2 cc3/p2.3 p2.4 13 p1.7/adc7/spi_clk/t0 rxd/p3.0 txd/p3.1 p2.5 p2.6 syncmos
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 5 - 32 pin lqfp cc0/txd/adc 1/p 1.1 cc1/t2/adc 2/p 1.2 cc 2/t2ex/adc3/p 1 .3 cc3/ss /adc4/p 1.4 mosi/ad c5/p1.5 int0/mis o/a dc6/p 1.6 t0/s pi_clk/a dc7/p 1.7 rxd/p 3.0 txd/p3.1 oci_sda/iic_sd a/trigadc/p3. 2 p 3.3/oci_s cl /iic_ scl p 2.0/cc 0 p 3 .4/reset p 3.5/xtal2/clkout p 0.4 /p wm4 p 2.1/cc 1 p 2.2/cc2 p 2.3/cc3 p 0.3 p 3 .6/xtal1 vss p 0.5/p wm 5 p0.6/int1/p wm6 p 0.7/t1/p wm7 p 2.6 rxd/adc 0/p 1.0 vdd p 0.0 p 0.1 p0.2 1 2 3 4 5 6 7 8 10 11 12 9 16 15 14 13 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 31 32 26 27 28 29 30 25 sm 39 r 16 a 6u 32vp yww (32 lqfp top view ) p2.4 p 2.5 notes (1) the pin reset/p3.4 factory default is gpio (p3.4). user can configure it to reset by a flash programmer. (2) to avoid accidentally entering isp - mode(refer to section 18.4), care must be taken not asserting pulse signal at rxd p 3 . 0 during power - up while p1. 2, p1.3 or p1.4 are set to high. (3) to apply icp function, o c i_sda/p 3.2 and oci _scl/p 3.3 are icp pins during reset period. when reset finish, they are gpio.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 6 - block diagram uart flash 16 kbytes sram 1kbytes sram 256bytes mdu interrupt timer 0/1 timer2 & ccu watchdog ice icp port 0 port 1 port 2 port 3 port 0 port 1 port 2 port 3 t0 t1 cc0~cc3 t2 t2ex iic_scl adc0 rxd txd interface control xtal1 xtal2 adc1 adc2 adc3 iic_sda spi spi_miso spi_mosi spi_clk spi_ss adc4 adc5 adc6 adc7 cpu adc iic oci_scl oci_sda max810 reset pwm pwm[7:4]
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 7 - pin description 32 l lqfp 28 l sop 24l sop symbol i/o description 1 24 21 p1.3/adc3/t 2ex / cc 2 i/o bit 3 of port 1 & adc input channel 3 & timer 2 capture trigger & timer 2 compare/capture c hannel 2 2 25 22 p1.4/adc4/ss/c c 3 i/o bit 4 of port 1 & adc input channel 4 & spi interface slave select pin & timer 2 compare/capture c hannel 3 3 26 23 p1.5/adc5/mosi i/o bit 5 of port 1 & adc inpu t channel 5 & spi interface serial data master output or slave input pin 4 27 24 p1.6/adc6/miso/ int0 i/o bit 6 of port 1 & adc input channel 6 & spi interface serial data master input or slave output pin & external interrupt 0 5 28 1 p1.7/adc7/spi_ clk/ t0 i/o bit 7 of port 1 & adc input channel 7 & spi interface clock pin & timer 0 external input 6 1 p3.0/rxd i/o bit 0 of por t 3 & serial interface channel r eceive data 7 2 p3.1/txd i/o bit 1 of port 3 & serial interface channel transmit data or receive clock in mode 0 8 3 2 p3.2/ trigadc/ii c_sda/oci_sda i/o bit 2 of port 3 & external pin to trigger adc & iic sda pin & on - chip instrumentation sda 9 4 3 p3.3/ iic_scl/oc i_scl i/o bit 3 of port 3 & iic scl pin & on - chip instrumentation scl 10 5 4 p3.4/ reset i/o bit 4 of port 3 & reset pin 11 6 5 p3.5/ xtal2/clk out i/o bit 5 of port 3 & crystal output & clock out 12 7 6 p3.6/ xtal1 i/o bit 6 of port 3 & crystal input 13 8 7 vss ground 14 9 8 p2.0 / cc0 i/o bit 0 of port 2 & timer 2 compare/capture channel 0 15 10 9 p2.1 / cc1 i/o bit 1 of port 2 & timer 2 compare/capture channel 1 16 11 10 p2.2/ cc2 i/o bit 2 of port 2 & timer 2 compare/capture channel 2 17 12 11 p2.3/ cc3 i/o bit 3 of port 2 & timer 2 compare/capture channel 3 18 13 p2.4 i/o bit 4 of port 2 19 14 p2.5 i/o bit 5 of port 2 20 15 12 p2.6 i/o bit 6 of port 2 21 16 13 p0.7/ pwm7/t1 i/o bit 7 of port 0 & pwm channel 7 & timer 1 external input 22 17 14 p0. 6 / pwm 6 / int1 i/o bit 6 of port 0 & pwm channel 6 & external interrupt 1 23 18 15 p0.5/ pwm5 i/o bit 5 of port 0 & pwm channel 5 24 19 16 p0.4/ pwm4 i/o bit 4 of port 0 & pwm channel 4 25 p0.3 i/o bit 3 of port 0 26 p0.2 i/o bit 2 of port 0 27 p0.1 i/o bit 1 of port 0 28 p0.0 i/o bit 0 of port 0 29 20 17 vdd i power supply 30 21 18 p1.0/adc0/ rxd i/o bit 0 of port 1 & adc input channe l 0 & serial interface channel receive data 31 22 19 p1.1/adc1/t xd / cc0 i/o bit 1 of port 1 & adc input channel 1 & serial inte rface channel transmit data & timer 2 compare/capture channel 0 32 23 20 p1.2/adc2/ t2/c c1 i/o bit 2 of port 1 & adc input channel 2 & timer 2 external input clock & timer 2 compare/capture channel 1
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 8 - special function register (sfr) a map of the special function registers is shown as below: in - direct access mode hex \ bin x 000 x001 x010 x011 x100 x101 x110 x111 bin/hex f8 iics iicctl iica1 iica2 iicrwd iic ebt ff f0 b spic1 spic2 spitxd spirxd spis takey f7 e8 md0 md 1 md 2 md 3 md 4 md 5 arcon ef e0 acc ispfah ispfal ispfd ispfc lv c swres e7 d8 pfcon p3m0 p3m1 df d0 psw ccen2 p0m0 p0m1 p1m0 p1m1 p2m0 p2m1 d7 c8 t2con cccon crcl crch tl2 th2 cf c0 ircon ccen ccl1 cch1 ccl2 cch2 ccl3 cch3 c7 b8 ien1 ip1 s relh pagese l bf b0 p3 wdtc wdtk b7 a8 ien0 ip0 s rell adcc1 adcc2 adcdh adcdl adccs af a0 p2 rsts pwm addr pwm data a7 98 s con s buf ien2 9f 90 p1 aux ircon2 97 88 tcon tmod tl0 tl1 th0 th1 ckcon ifcon 8f 80 p0 sp dpl dph dpl1 dph1 rcon pcon 87 hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 9 - page mode: page0 hex \ bin x000 x0 01 x010 x011 x100 x101 x110 x111 bin/hex f8 iics iicctl iica1 iica2 iicrwd iic ebt ff f0 b spic1 spic2 spitxd spirxd spis takey f7 e8 md0 md1 md2 md3 md4 md5 arcon ef e0 acc ispfah ispfal ispfd ispfc lv c swres e7 d8 pfcon p3m0 p3m1 df d0 psw ccen2 p0m0 p0m1 p1m0 p1m1 p2m0 p2m1 d7 c8 t2con cccon crcl crch tl2 th2 oppin2 cmp2co n cf c0 ircon ccen ccl1 cch1 ccl2 cch2 ccl3 cch3 c7 b8 ien1 ip1 s relh pagese l bf b0 p3 wdtc wdtk b7 a8 ien0 ip0 s rell adcc1 adcc2 adcdh adcdl adccs af a0 p2 rsts a7 98 s con s buf ien2 9f 90 p1 aux ircon2 97 88 tcon tmod tl0 tl1 th0 th1 ckcon ifcon 8f 80 p0 sp dpl dph dpl1 dph1 rcon pcon 87 hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex page mode: page1 hex \ bin x000 x 001 x010 x011 x100 x101 x110 x111 bin/hex f8 pwmtbc 0 pwmtbc 1 pwmop mod ff f0 b periodl periodh pwmen takey f7 e8 pwmtb post scale ef e0 acc ispfah ispfal ispfd ispfc lv c swres e7 d8 pfcon pwmpol arity df d0 psw duty2l du ty2h duty3l d7 c8 t2con duty3h tl2 th2 cf c0 ircon c7 b8 ien1 ip1 srelh pwmint f pagesel bf b0 p3 wdtc wdtk b7 a8 ien0 ip0 srell adcc1 adcc2 adcdh adcdl adccs af a0 p2 a7 98 scon sbuf ien2 9f 90 p1 aux ircon2 97 88 tcon tmod tl0 tl1 th0 th1 ckcon ifcon 8f 80 p0 sp dpl dph dpl1 dph1 rcon pcon 87 hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 10 - note: special function registers reset values and description for SM39R16A6 . register location: 80h ~ 8fh re set value description method 1 method 2 page 0 method 2 page 1 system sp 81h 81h 81h 07h stack pointer acc e0h e0h e0h 00h accumulator psw d0h d0h d0h 00h program status word b f0h f0h f0h 00h b register dpl 82h 82h 82h 00h data pointer 0 low byt e dph 83h 83h 83h 00h data pointer 0 high byte dpl1 84h 84h 84h 00h data pointer 1 low byte dph1 85h 85h 85h 00h data pointer 1 high byte aux 91h 91h 91h 00h auxiliary register pcon 87h 87h 87h 4 0h power control ckcon 8eh 8eh 8eh 10h clock control re gister pagesel beh beh beh 00h page select interrupt & priority ircon c0h c0h c0h 00h interrupt request control register ircon2 97h 97h 97h 00h interrupt request control register 2 ien0 a8h a8h a8h 00h interrupt enable register 0 ien1 b8h b8h b8h 00h interrupt enable register 1 ien2 9ah 9ah 9ah 00h interrupt enable register 2 ip0 a9h a9h a9h 00h interrupt priority register 0 ip1 b9h b9h b9h 00h interrupt priority register 1 uart pcon 87h 87h 87h 4 0h power control aux 91h 91h 91h 00h auxiliary re gister scon 98h 98h 98h 00h serial port, control register sbuf 99h 99h 99h 00h serial port, data buffer srell aah aah aah 00h serial port, reload register, low byte srelh bah bah bah 00h serial port, reload register, high byte pfcon d9h d9h d9h 00h pe ripheral frequency control register adc adcc1 abh abh abh 00h adc control 1 register adcc2 ach ach ach 0 8 h adc control 2 register adcdh adh adh adh 00h adc data high byte adcdl aeh aeh aeh 00h adc data low byte adccs afh afh afh 00h adc clock select wdt rsts a1h a1h 00h reset status register wdtc b6h b6h b6h 04h watchdog timer control register
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 11 - register location: 80h ~ 8fh re set value description method 1 method 2 page 0 method 2 page 1 wdtk b7h b7h b7h 00h watchdog timer refresh key. takey f7h f7h f7h 00h time access key register pwm p wm tbc0 f9 h 00h pwm time base control 0 reg. pwm t bc1 fa h 10h pwm time base control 1 reg. pwm opmod fb h 00h pwm output pair mode reg. periodl f1 h ff h pwm period (low) reg. periodh f2 h 3f h pwm period (high) reg. pwm en f5 h 00h pwm output enable reg. pwmtbpost scale ee h 00h pwm t ime b ase p os t s cale reg. pwmintf bch 00 h pwm int flag reg. pwmpolarity dd h ff h pwm polarity reg. d uty2l d5 h 00 h pwm 2 d uty low byte reg. duty2h d6 h 00 h pwm 2 d uty h igh byte reg. d uty3l d7 h 00 h pwm 3 d uty low byte reg. duty3h c9 h 00 h pwm 3 d uty h igh b yte reg. pwm addr a2 h 00 h pwm address register pwm data a3 h 00 h pwm data register timer0/timer1 tcon 88h 88h 88h 00h timer/counter control tmod 89h 89h 89h 00h timer mode control tl0 8ah 8ah 8ah 00h timer 0, low byte tl1 8bh 8bh 8bh 00h timer 1, l ow byte th0 8ch 8ch 8ch 00h timer 0, high byte th1 8dh 8dh 8dh 00h timer 1, high byte pfcon d9h d9h d9h 00h peripheral frequency control register pca(timer2) ccen c1h c1h 00h compare/capture enable register ccl1 c2h c2h 00h compare/capture register 1, low byte cch1 c3h c3h 00h compare/capture register 1, high byte ccl2 c4h c4h 00h compare/capture register 2, low byte cch2 c5h c5h 00h compare/capture register 2, high byte ccl3 c6h c6h 00h compare/capture register 3, low byte cch3 c7h c7h 00h compare/capture register 3, high byte t2con c8h c8h c8h 00h timer 2 control cccon c9h c9h 00h compare/capture control crcl cah cah 00h compare/reload/capture register, low byte
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 12 - register location: 80h ~ 8fh re set value description method 1 method 2 page 0 method 2 page 1 crch cbh cbh 00h co mpare/reload/capture register, high byte tl2 cch c ch cch 00h timer 2, low byte th2 cdh cdh cdh 00h timer 2, high byte ccen2 d1h d1h 00h compare/capture enable 2 register gpio p0 80h 80h 80h u ser define port 0 p1 90h 90h 90h ffh port 1 p 2 a0h a0h a0h 7 fh port 2 p3 b0h b0h b0h 7 fh port 3 p0m0 d2h d 2h user define port 0 output mode 0 p0m1 d3h d3h 00h port 0 output mode 1 p1m0 d4h d4h 00h port 1 output mode 0 p1m1 d5h d5h 00h port 1 output mode 1 p2m0 d6h d6 h 00h port 2 output mode 0 p2m1 d7h d7 h 00h port 2 output mode 1 p3m0 dah dah 00h port 3 output mode 0 p3m1 dbh dbh 00h port 3 output mode 1 isp/iap/eeprom ifcon 8fh 8fh 8fh 00h interface control register ispfah e1h e1h e1h ffh isp flash address - high register ispfal e2h e2h e2h ffh isp flash address - low register ispfd e3h e3h e3h ffh isp flash data register ispfc e4h e4h e4h 00h isp flash control register takey f7h f7h f7h 00h time access key register lvi/lvr/softreset rsts a1h a1h 00h reset status register lvc e6h e6h e6h 20h low voltage control register swres e7h e7h e7h 00h software reset register takey f7h f7h f7h 00h time access key register spi spic1 f1h f1h 08h spi control register 1 spic2 f2h f2h 00h spi control register 2 spitxd f3h f3h 00h spi transmit data buffer spirxd f4h f4h 00h spi receive data buffe r spis f5h f5h 40h spi status register iic iics f8h f8h 00h iic status register iicctl f9h f9h 04h iic control register
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 13 - register location: 80h ~ 8fh re set value description method 1 method 2 page 0 method 2 page 1 iica1 fah fah a0h iic channel 1 address 1 register iica2 fbh fbh 60h iic channel 1 address 2 register iicrwd fch fch 00h ii c channel 1 read / write data buffer iicebt fdh fdh 00h iic enable bus transaction register
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 14 - function description 1. general features SM39R16A6 is an 8 - bit micro - controller. all of its functions and the detailed meanings of sfr will be g iven in the follo wing sections. 1.1 embedded flash the program can be loaded into the embedded 16 kb flash memory via its writer or in - system programming (isp). the high - quality flash suitable for re - programmin g and data recording as eeprom. 1.2 io pads the SM39R16A6 has four i/o p orts: port 0, port 1, port 2 and port 3. ports 0, 1 are 8 - bit ports and port 2, 3 are 7 - bit port s . these are: quasi - bidirectional (standard 8051 port outputs), push - pull, open drain, and input - onl y. as description in section 5. all the pads for p0 , p1 , p2 and p3 are with slew rate to reduce emi. the io pads can withstand 4kv esd in human body mode guaranteeing the SM39R16A6 ?s quality in hi gh electro - static environments. the reset pin can define as general i/o p 3 . 4 when user use internal reset. the xtal2 and xtal1 can define as p3. 5 and p3. 6 by writer or isp when user use internal osc as system clock . w hen user use external osc as system clock and input into xtal1 , o nly xtal2 can be defined as p3. 5 . 1.3 instruction timing selection the conventional 52 - series mcus are 12t, i.e., 12 oscillator clocks per machine cycle. SM39R16A6 is a 1t to 8t mcu, i.e., its machine cycle is one - clock to eight - clock. in the other words, it can execute one instruction within one clock to only eight clocks. mnemonic: ckcon address: 8e h 7 6 5 4 3 2 1 0 reset - its[2:0] - - clkout[1:0] 10h its: instruction timing select. its [2:0] instruction timing 000 1t mode 001 2t mode (default) 010 3t mode 011 4t mode 100 5t mode 101 6t mode 110 7t mode 111 8t mode the default i s in 2t mode, and it can be changed to another instruction timing mode if ckcon [6:4] (at address 8eh) is change any time. not every instruction can be executed with one machine cycle. the exact machine cycle number for all the instructions are given in th e next section.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 15 - 1.4 clock out selection the SM39R16A6 can g enerat e a clock out signal at p3. 5 when user use oscillator (xtal1 as clock input) or internal osc as system clock. the ckcon [1:0] (at address 8eh) can change any time. clkout: clock output select. ckcon [1:0] mode. 00 gpio(default) 01 fosc 10 fosc/2 11 fosc/4 1.5 reset 1.5.1 hardware reset function SM39R16A6 provides internal reset circuit inside , the internal reset time can set by writer or isp. internal reset time 25ms (default) 200ms 100ms 50m s 16ms 8ms 4ms 1.5.2 software reset function SM39R16A6 provides one software reset mechanism to reset whole chip. to perform a software reset, the firmware must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the s oftware reset register (swres) write attribute. after swres register obtain the write authority, the firmware can write ffh to the swres register. the hardware will decode a reset signal that ?or? with the other hardware reset. the swres register is self - r eset at the end of the software reset procedure. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst software reset function rsts reset status register a1h - lvrlp intf lvrlp f pdrf wdtf swrf lvrf porf 00h takey time access k ey register f7h takey [7:0] 00h swres software reset register e7h swres [7:0] 00h
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 16 - 1.5.3 reset status mnemonic: rsts address: a1h 7 6 5 4 3 2 1 0 reset - lvrlp intf lvrlpf pdrf wdtf swrf lvrf porf 00h lvr lpint f : ? internal ? low voltage reset flag. when m cu is reset by lvr_lp_int , lvrlpintf flag will be set to one by hardware. this flag clear by software . lvrlpf : low voltage reset (low power) flag. when mcu is reset by lvr (low power) , lvrlpf flag will be set to one by hardware. this flag clear by softwar e . pdrf: pad reset flag. when m cu is reset by reset pad , pdr f flag will be set to one by hardware. this flag clear by software. wdtf: watchdog timer reset flag. w h en mcu is reset by watchdog, wdtf flag will be set to one by hardware. this flag clear by s oftware. swrf: software reset flag. when mcu is reset by software , swrf flag will be set to one by hardware. this flag clear by software . lvrf: low voltage reset flag. when mcu is reset by lvr , lvrf flag will be set to one by hardware. this flag clear by software . porf: power on reset flag. when mcu is reset by por , porf flag will be set to one by hardware. this flag clear by software . 1.5.4 time access key register (takey) mnemonic: takey address:f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h software reset register (swres) is read - only by default, software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the swres register write attribute. that is: mov tak ey, #55h mov takey, #0aah mov takey, #5ah
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 17 - 1.5.5 software reset register (swres) swres [7:0]: software reset register bit. these 8 - bit i s self - reset at the end of the reset procedure. swres [7:0] = ffh, software reset. swres [7:0] = 00h ~ feh, mcu no action. 1.5.6 example of software reset mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable swres write attribute mov swres, #0ffh ; sof tware reset mcu 1.6 clocks the default clock is the 22.1184mhz internal osc. this clock is used during the initialization stage. the major work of the initialization stage is to determine the clock source used in normal operation. the internal clock sources a re from the internal osc with difference frequ ency division as shown in table 1 - 1 , the clock source can set by writer. table 1 - 1 : selection of clock source clock source external cr ystal (use xtal1 and xtal2 pins ) external crystal (only use xtal1, the xtal2 define as i/o) 22.1184mhz from internal osc 11.0592 mhz from internal osc 5.5296 mhz from internal osc 2.7648 mhz from internal osc 1.3824 mhz from internal osc there may be having a little variance in the frequency from the internal osc. the max variance as giving in table 1 - 2 . table 1 - 2 : temperature with variance temperature max variance 25 2 % mnemonic: swres address: e7h 7 6 5 4 3 2 1 0 reset swres [7:0] 00h
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 18 - 2. instruction set a ll SM39R16A6 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051. the following tables give a summary of the instruction set cycles of the SM39R16A6 microcontroller core. table 2 - 1 : arithmetic operations mnemonic description code bytes cycles add a,rn add register to accumulator 28 - 2f 1 1 add a,direct add direct byte to accumulator 25 2 2 add a,@ri add indirect ram to accumulator 26- 27 1 2 add a,#data add immediate data to accumulator 24 2 2 addc a,rn add register to accumulator with carry flag 38 - 3f 1 1 addc a,direct add direct byte to a with carry flag 35 2 2 addc a,@ri add indirect ram to a with carry flag 36- 37 1 2 addc a ,#data add immediate data to a with carry flag 34 2 2 subb a,rn subtract register from a with borrow 98 - 9f 1 1 subb a,direct subtract direct byte from a with borrow 95 2 2 subb a,@ri subtract indirect ram from a with borrow 96- 97 1 2 subb a,#data subtr act immediate data from a with borrow 94 2 2 inc a increment accumulator 04 1 1 inc rn increment register 08 - 0f 1 2 inc direct increment direct byte 05 2 3 inc @ri increment indirect ram 06 - 07 1 3 inc dptr increment data pointer a3 1 1 dec a decremen t accumulator 14 1 1 dec rn decrement register 18- 1f 1 2 dec direct decrement direct byte 15 2 3 dec @ri decrement indirect ram 16 - 17 1 3 mul ab multiply a and b a4 1 5 div divide a by b 84 1 5 da a decimal adjust accumulator d4 1 1
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 19 - table 2 - 2 : logic operations mnemonic description code bytes cycles anl a,rn and register to accumulator 58 - 5f 1 1 anl a,direct and direct byte to accumulator 55 2 2 anl a,@ri and indirect ram to accumulator 56 - 57 1 2 an l a,#data and immediate data to accumulator 54 2 2 anl direct,a and accumulator to direct byte 52 2 3 anl direct,#data and immediate data to direct byte 53 3 4 orl a,rn or register to accumulator 48 - 4f 1 1 orl a,direct or direct byte to accumulator 45 2 2 orl a,@ri or indirect ram to accumulator 46 - 47 1 2 orl a,#data or immediate data to accumulator 44 2 2 orl direct,a or accumulator to direct byte 42 2 3 orl direct,#data or immediate data to direct byte 43 3 4 xrl a,rn exclusive or register to acc umulator 68 - 6f 1 1 xrl a,direct exclusive or direct byte to accumulator 65 2 2 xrl a,@ri exclusive or indirect ram to accumulator 66 - 67 1 2 xrl a,#data exclusive or immediate data to accumulator 64 2 2 xrl direct,a exclusive or accumulator to direct by te 62 2 3 xrl direct,#data exclusive or immediate data to direct byte 63 3 4 clr a clear accumulator e4 1 1 cpl a complement accumulator f4 1 1 rl a rotate accumulator left 23 1 1 rlc a rotate accumulator left through carry 33 1 1 rr a rotate accumul ator right 03 1 1 rrc a rotate accumulator right through carry 13 1 1 swap a swap nibbles within the accumulator c4 1 1
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 20 - table 2 - 3 : data transfer mnemonic description code bytes cycles mov a,rn move regis ter to accumulator e8 - ef 1 1 mov a,direct move direct byte to accumulator e5 2 2 mov a,@ri move indirect ram to accumulator e6 - e7 1 2 mov a,#data move immediate data to accumulator 74 2 2 mov rn,a move accumulator to register f8 - ff 1 2 mov rn,direct m ove direct byte to register a8 - af 2 4 mov rn,#data move immediate data to register 78 - 7f 2 2 mov direct,a move accumulator to direct byte f5 2 3 mov direct,rn move register to direct byte 88 - 8f 2 3 mov direct1,direct2 move direct byte to direct byte 85 3 4 mov direct,@ri move indirect ram to direct byte 86 - 87 2 4 mov direct,#data move immediate data to direct byte 75 3 3 mov @ri,a move accumulator to indirect ram f6 - f7 1 3 mov @ri,direct move direct byte to indirect ram a6 - a7 2 5 mov @ri,#data move immediate data to indirect ram 76- 77 2 3 mov dptr,#data16 load data pointer with a 16 - bit constant 90 3 3 movc a,@a+dptr move code byte relative to dptr to accumulator 93 1 3 movc a,@a+pc move code byte relative to pc to accumulator 83 1 3 movx a,@ri move external ram (8 - bit addr.) to a e2 - e3 1 3 movx a,@dptr move external ram (16 - bit addr.) to a e0 1 3 movx @ri,a move a to external ram (8 - bit addr.) f2 - f3 1 4 movx @dptr,a move a to external ram (16 - bit addr.) f0 1 4 push direct push direct byte on to stack c0 2 4 pop direct pop direct byte from stack d0 2 3 xch a,rn exchange register with accumulator c8 - cf 1 2 xch a,direct exchange direct byte with accumulator c5 2 3 xch a,@ri exchange indirect ram with accumulator c6 - c7 1 3 xchd a,@ri exchange low - order nibble indir. ram with a d6 - d7 1 3
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 21 - table 2 - 4 : program branches mnemonic description code bytes cycles acall addr11 absolute subroutine call xxx11 2 6 lcall addr16 long subroutine call 12 3 6 r et from subroutine 22 1 4 reti from interrupt 32 1 4 ajmp addr11 absolute jump xxx01 2 3 ljmp addr16 long iump 02 3 4 sjmp rel short jump (relative addr.) 80 2 3 jmp @a+dptr jump indirect relative to the dptr 73 1 2 jz rel jump if accumulator is zero 60 2 3 jnz rel jump if accumulator is not zero 70 2 3 jc rel jump if carry flag is set 40 2 3 jnc jump if carry flag is not set 50 2 3 jb bit,rel jump if direct bit is set 20 3 4 jnb bit,rel jump if direct bit is not set 30 3 4 jbc bit,direct rel ju mp if direct bit is set and clear bit 10 3 4 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 4 cjne a,#data rel compare immediate to a and jump if not equal b4 3 4 cjne rn,#data rel compare immed. to reg. and jump if not equal b8 - b f 3 4 cjne @ri,#data rel compare immed. to ind. and jump if not equal b6 - b7 3 4 djnz rn,rel decrement register and jump if not zero d8 - df 2 3 djnz direct,rel decrement direct byte and jump if not zero d5 3 4 nop no operation 00 1 1 table 2 - 5 : boolean manipulation mnemonic description code bytes cycles clr c clear carry flag c3 1 1 clr bit clear direct bit c2 2 3 setb c set carry flag d3 1 1 setb bit set direct bit d2 2 3 cpl c complement carr y flag b3 1 1 cpl bit complement direct bit b2 2 3 anl c,bit and direct bit to carry flag 82 2 2 anl c,/bit and complement of direct bit to carry b0 2 2 orl c,bit or direct bit to carry flag 72 2 2 orl c,/bit or complement of direct bit to c arry a0 2 2 mov c,bit move direct bit to carry flag a2 2 2 mov bit,c move carry flag to direct bit 92 2 3
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 22 - 3. memory structure the SM39R16A6 memory structure follows general 8052 structure. it is integrate the expanded 1kb data memory and 16kb progr am memory. 3.1 program memory the SM39R16A6 has 16 kb on - chip flash memory which can be used as general program memory or eeprom, on which include up to 1 k byte specific isp service program memory space. the address range for the 16 k byte is $0000 to $ 3 fff. th e address range for the isp service program is $ 3c 00 to $ 3 fff. the isp service program size can be partitioned as n blocks of 128 byte (n=0 to 8 ). when n=0 means no isp service program space available, total 16 k byte memory used as program memory. when n = 1 means address $ 3 f 8 0 to $ 3 fff reserved for isp service program. when n=2 means memory address $ 3f 00 to $ 3 fff reserved for isp service program?etc. value n can be set and programmed into SM39R16A6 information block by writer. as shown in fig. 3 - 1 3fff 3f80 3f00 3e80 3e00 3d80 3d00 3c80 3c00 0000 isp service program space, up to 1k 16k program memory space n=8 n=7 n=6 n=5 n=4 n=3 n=2 n=1 n=0 fig. 3 - 1 : SM39R16A6 programmable flash
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 23 - 3.2 data memory the SM39R16A6 has 1 k + 256b on - chip sram, 256b of it are the same as general 8052 internal memory structur e while the expanded 1 k bytes on - chip sram can be accessed by external memory addressing method ( by instruction movx.) . as shown in fig. 3 - 2 higher 128 bytes (accessed by indirect addressing mode only) lower 128 bytes (accessed by direct & indirect addressing mode ) sfr (accessed by direct addressing mode only) expanded 1k bytes (accessed by direct external addressing mode by instruction movx) 00 7f 80 ff 80 ff 0000 03ff fig. 3 - 2 : ram architecture 3.3 data memory - lower 128 byte (00h to 7fh) data memory 00h to ffh is the same as 8052. the address 00h to 7fh can be accessed by direct and indirect addressing modes. address 00h to 1fh is register area. address 20h to 2fh is memory bit a rea. address 30h to 7fh is for general memory area. 3.4 data memory - higher 128 byte (80h to ffh) the address 80h to ffh can be accessed by indirect addressing mode. address 80h to ffh is data area. 3.5 data memory - expanded 1 k bytes ( 0000h ~ 03ff h) from extern al address 0000h to 03ffh is the on - chip expanded sram area, total 1k bytes. this area can be accessed by external direct addressing mode (by instruction movx). the address space of instruction movx @ri, i=0, 1 is determined by rcon [7:0] of special functi on register $86 rcon (internal ram control register). the default setting of rcon [7:0] is 00h (page0). one page of data ram is 256 bytes. note: sm39 r 16a6 can not access (off - chip) external ram. movx @ri, a movx a, @ri 0 Q rcon[7:0] Q 3 addr [15:8] <= r con[7:0]
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 24 - 4. cpu engine the SM39R16A6 engine is composed of four components: (1) control unit (2) arithmetic ? logic unit (3) memory control unit (4) ram and sfr control unit the SM39R16A6 engine allows to fetch instruction from program memory and to execute u sing ram or sfr. the following chapter describes the main engine register. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst 8051 core acc accumulator e0h acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00h b b register f0h b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h psw program status word d0h cy ac f0 rs[1:0] ov psw.1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 0 82h dpl[7:0] 00h dph data pointer high 0 83h dph[7:0] 00h dpl1 data pointer low 1 84h dpl1[7:0] 00 h dph1 data pointer high 1 85h dph1[7:0] 00h aux auxiliary register 91h b r g s p21cc - p1ur - - - dps 00h ckcon clock control register 8eh - its[2:0] - - clkout[1:0] 10h ifcon interface control register 8fh - cdpr - - - - - ispe 00h pagesel page selec t beh - - - - - - p age _ num p age _ mode 00h 4.1 accumulator acc is the accumulator register. most instructions use the accumulator to store the operand. mnemonic: acc address: e0h 7 6 5 4 3 2 1 0 reset acc.7 acc.6 acc05 acc.4 acc.3 acc.2 acc.1 acc.0 00h acc[7:0]: the a (or acc) register is the standard 8052 accumulator. 4.2 b register the b register is used during multiply and divide instructions. it can also be used as a scratch pad register to store temporary data. mnemonic: b address: f0h 7 6 5 4 3 2 1 0 reset b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h b[7:0]: the b register is the standard 8052 register that serves as a second accumulator.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 25 - 4.3 program status word mnemonic: psw address: d0h 7 6 5 4 3 2 1 0 reset cy ac f0 rs [1:0] ov f1 p 00h cy: carry fla g. ac: auxiliary carry flag for bcd operations. f0: general purpose flag 0 available for user. rs[1:0]: register bank select, used to select working register bank. rs[1:0] bank selected location 00 bank 0 00h ? 07h 01 bank 1 08h ? 0fh 10 bank 2 10h ? 17h 11 bank 3 18h ? 1fh ov: overflow flag. f1: general purpose flag 1 available for user. p: parity flag, affected by hardware to indicate odd/even number of ?one? bits in the accumulator, i.e. even parity. 4.4 stack pointer the stack pointer is a 1 - by te register initialized to 07h after reset. this register is incremented before push and call instructions, causing the stack to start from location 08h. mnemonic: sp address: 81h 7 6 5 4 3 2 1 0 reset sp [7:0] 07h sp[7:0]: the stack pointer stores t he scratchpad ram address where the stack begins. in other words, it always points to the top of the stack. 4.5 data pointer the data pointer (dptr) is 2 - bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2 - byte register (e.g. m ov dptr, #data16) or as two separate registers (e.g. mov dpl,#data8). it is generally used to access the external code or d ata space (e.g. movc a, @a+dptr or movx a, @dptr respectively). mnemonic: dpl address: 82h 7 6 5 4 3 2 1 0 reset dpl [7:0] 00h d pl[7:0]: data pointer low 0 mnemonic: dph address: 83h 7 6 5 4 3 2 1 0 reset dph [7:0] 00h dph [7:0]: data pointer high 0
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 26 - 4.6 data pointer 1 the dual data pointer accelerates the moves of data block. the standard dptr is a 16 - bit register that is used to address external memory or peripherals. in the SM39R16A6 core the standard data pointer is called dptr, the second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data pointer select bit is located in lsb of aux register (dps). the user switches between pointers by toggling the lsb of aux register. all dptr - related instructions use the currently selected dptr for any activity. mnemonic: dpl1 address: 84h 7 6 5 4 3 2 1 0 reset dpl1 [7:0] 00h dpl1[7:0]: data p ointer low 1 mnemonic: dph1 address: 85h 7 6 5 4 3 2 1 0 reset dph1 [7:0] 00h dph1[7:0]: data pointer high 1 mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs p21cc - p1ur - - - dps 00h dps: data pointer select register. dps = 1 is selected dptr1. 4.7 clock control register mnemonic: ckcon address: 8eh 7 6 5 4 3 2 1 0 reset - its[2:0] - - clkout[1:0] 10h its[2:0]: instruction timing select. its [2:0] mode 000 1t mode 001 2t mode (default) 010 3t mode 011 4t mode 100 5t mode 101 6t mo de 110 7t mode 111 8t mode clkout[1:0]: clock output select. clkout[1:0] mode 00 gpio(default) 01 fosc 10 fosc/2 11 fosc/4 it can be used when the system clock is the internal rc oscillator.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 27 - 4.8 interface control register mnemonic: ifcon address: 8 fh 7 6 5 4 3 2 1 0 reset - cdpr - - - - - ispe 00h cdpr: code protect (read only) ispe: isp function enable bit ispe = 1, enable isp function ispe = 0, disable isp function 4.9 pagesel (page select) the sm 39r16a6 provide two different methods to set special function register (sfr) are as follow: ? sfr method 1 (indirect mode): this method is only an sfr page. if you want to use pwm registers of the method 2, can be used indirectly addressable setting. example: write a data 0x80h to pwmen register in method 1. pagesel = 0 x0 0 ; // method 1. pwmaddr = 0 xf5 ; // pwmen indirect address: 0xf5 (indirect mode) // (refer page1 table of the method 2) pwmdata = 0 x80 ; // write data 0x80 to pwmen. ? sfr method 2 (page mode): this m ethod provides two sfr page to set the registers. example: write a data 0x80 to pwmen register in method 2, page 1. pagesel = 0 x 0 3 ; // method 2, page 1 (page mode) pwmen = 0 x80; // write data 0x80 to pwmen. ? sfr page mode table: page_mode page_num sf r select 0 0 sfr method 1 0 1 sfr method 1 1 0 sfr method 2, page 0 1 1 sfr method 2, page 1 mnemonic: pagesel address: b eh 7 6 5 4 3 2 1 0 reset - - - - - - p age _ num p age _ mode 0 0h page_num : this flag is used only in the sfr method 2 0 = pa ge 0 mode . 1 = page 1 mode. page_mode : this flag is used to select sfr register table.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 28 - 0 : sfr method 1 (indirect mode) . 1 : sfr method 2 (page mode).
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 29 - 5. gpio 5.1 sfr setting method the SM39R16A6 has four i/o ports: port 0, port 1 , port 2, port 3. ports 0, 1 , 2 are 8 - bit ports and ports 2 , 3 are 7 - bit ports. these are: quasi - bidirectional (standard 8 0 51 port outputs), push - pull, open drain, and input - only. two configuration registers for each port select the output type for each port pin. all i/o port pins on the SM39R16A6 may be configured by software to one fo four types on a pin - by - pin basis, shown as below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset i/o port function register p0m0 port 0 output mode 0 d2h p0m0 [7: 0] ~ op18 p0m1 port 0 output mode 1 d3h p0m1[7:0] 00h p1m0 port 1 output mode 0 d4h p1m0[7:0] 00h p1m1 port 1 output mode 1 d5h p1m1[7:0] 00h p2m0 port 2 output mode 0 d6h - p2m0[6:0] 00h p2m1 port 2 output mode 1 d7h - p2m1[6:0] 00h p3m0 port 3 output mode 0 dah - p3m0[6:0] 00h p3m1 port 3 output mode 1 dbh - p3m1[6:0] 00h *op18 by writer programming set. pxm1.y pxm0.y port output mode 0 0 quasi - bidirectional (standard 8051 port outputs) (pull - up) 0 1 push - pull 1 0 input only (high - imped ance) 1 1 open drain the reset pin can define as general i/o p 3 . 4 when user use internal reset. the xtal2 and xtal1 can define as p3. 5 and p3. 6 by writer when user use internal osc as system clock . w hen user use external osc as system clock and input int o xtal1 , o nly xtal2 can be defined as p3. 5 . for general - purpose applications, every pin can be assigned to either high or low independently . as shown below: mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst ports port 3 por t 3 b0h - p 3 .6 p 3 .5 p 3 .4 p 3 .3 p 3 .2 p 3 .1 p 3 .0 7 fh port 2 port 2 a 0h - p 2 .6 p 2 .5 p 2 .4 p 2 .3 p 2 .2 p 2 .1 p 2 .0 7 fh port 1 port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh port 0 port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 op19 *op19 b y writer pr ogramming set.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 30 - mnemonic: p0 address: 80h 7 6 5 4 3 2 1 0 reset p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 op19 p0.7~ 0: port0 [7] ~ port0[0] mnemonic: p1 address: 90h 7 6 5 4 3 2 1 0 reset p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh p1.7~ 0: port1 [7] ~ port1 [0] mnemonic: p 2 address: a 0h 7 6 5 4 3 2 1 0 reset - p 2 .6 p 2 .5 p 2 .4 p 2 .3 p 2 .2 p 2 .1 p 2 .0 7 fh p2. 6 ~ 0: port 2 [ 6 ] ~ port 2 [0] mnemonic: p 3 address: b 0h 7 6 5 4 3 2 1 0 reset - p 3 .6 p 3 .5 p 3 .4 p 3 .3 p 3 .2 p 3 .1 p 3 .0 7 fh p 3 . 6 ~ 0: port 3 [ 6 ] ~ port 3 [0] 5.2 software of writer setting method please setting the ?io output mode" item in the "configuration" window, it can change the i/o mode of p1~ p3 to the quasi - bidirectional (standard 8051 port outputs) (pull - up)? or input only (high - impedance) mode, when mcu after reset and initial. it is supported the version d of mcu after.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 31 - 6. multiplication division unit this on - chip arithmetic unit provides 32 - bit division, 16 - bit multiplication, shift and normalize features. all operations are unsigned integer operation. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset multiplication division unit pcon power control 87h smod mdu f - - - - stop idle 40h arcon arithmetic control register efh mdef mdov slr sc[4:0] 00h md0 multiplication/divi sion register 0 e9h md0[7:0] 00h md1 multiplication/divi sion register 1 eah md1[7:0] 00h md2 multiplication/divi sion register 2 ebh md2[7:0] 00h md3 multiplication/divi sion register 3 ech md3[7:0] 00h md4 multiplication/divi sion register 4 edh md4[7:0] 00h md5 multiplication/divi sion register 5 eeh md5[7:0] 00h 6.1 operating registers of the mdu the mdu is handled by eight registers, which are memory mapped as special function registers. the arithmetic unit allows operations concurrently to and independent of the cpu?s activity. operands and results registers are md0 to md5. control register is arcon. any calculation of the mdu overwrites its op erands. mnemonic: arcon address: efh 7 6 5 4 3 2 1 0 reset mdef mdov slr sc[4:0] 00h mdef - multiplocation division errot flag. the mdef is an error flag. the error flag is read only. the error flag indicates an improperly performed operation (when one of the arithmetic operations has been restarted or interrupted by a new operation). the error flag mechanism is automatically enabled with the first write to md0 and disabled with the final read instruction from md3 multiplication or shift/normalizing) or md5 (division) in phase three. the error flag is set when: 1. phase two in process and write access to md x registers (restart or interrupt calculations) the error flag is reset only if: the second p hase two finished (arithmetic operation successful completed ) and read access to mdx registers. mdov - multiplication division overflow flag. the overflow flag is read only. the overflow flag is set when: 1. division by zero 2. multiplication with a result greater then 0000ffffh
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 32 - 3. start of normalizing if the most signific ant bit of md3 is set(md3.7 = 1) the overflow flag is reset when: write access to md0 register (start phase one) slr - shift direction bit. slr = 0 ? shift left operation. slr = 1 ? shift right operation. sc[4:0] - shift counter. when preset with 00000b, n ormalizing is selected. after normalize sc.0 ? sc.4 contains the number of normalizing shifts performed. when sc.4 ? sc.0 0, shift - operation is started. the number of shifts performed is determined by the count written to sc.4 to sc.0. sc.4 ? msb ... sc .0 ? lsb 6.2 operation of the mdu operations of the mdu consist of three phases: 6.2.1 first phase: loading the mdx registers. the type of calculation the mdu has to perform is selected following the order in which the mdx registers are written to. table 6 - 1 mdu registers write sequence operation 32bit/16bit 16bit/16bit 16bit x 16bit shift/normalizing first write md0 dividend low md0 dividend low md0 multiplicand low md0 lsb md1 dividend md1 dividend high md4 multiplicator low md1 md2 dividen d md1 multiplicand high md2 md3 dividend high md3 msb md4 divisor low md4 divisor low last write md5 divisor high md5 divisor high md5 multiplicator high arcon start conversion a write to md 0 is the first transfer to be done in any case. next w rites must be done as shown in table 6 - 1 to determine mdu operation. last write finally starts selected operation. 6.2.2 second phase: executing calculation. during executing operation, the mdu works on its own parallel to the cpu. when mdu is finished, the mduf register will be set to one by hardware and the flag will clear at next calculation. mnemonic: pcon address: 87h 7 6 5 4 3 2 1 0 reset smod mduf stop idle 4 0h mduf: mdu finish flag. when mdu is finished, the mduf will be set by hardware and the bit will clear by hardware at next calculation. table 6 - 2 mdu execution times operation number of tclk division 32bit/16bit 17 clock cycles division 16bit/16bit 9 clock cycles multiplication 11 clock cycles
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 33 - shift min 3 clock cycles , max 18 clock cycles normalize min 4 clock cycles , max 19 clock cycles 6.2.3 third phase: reading the result from the mdx registers. read out sequence of the first mdx registers is not critical but the last read (from md5 - divisio n and md3 - multiplication, shift and normalizing) determines the end of a whole calculation (end of phase three). table 6 - 3 mdu registers read sequence operation 32bit/16bit 16bit/16bit 16bit x 16bit shift/normalizing first read md0 q uotien t low md0 quotien low md0 product low md0 lsb md1 quotien t md1 quotien high md1 product md1 md2 quotien t md2 product md2 md3 quotien t high md4 remainder l md4 remainder low last read md5 remainder h md5 remainder high md3 prod uct high md3 msb 6.3 normalizing all reading zeroes of integer s variables in registers md0 to md3 are removed by shift left operations. the whole operation is completed when the msb (most significant bit) of md3 register contains a ?1?. after normalizing, b its arcon.4 (msb) to arcon.0 (lsb) contain the number of shift left operations, which were done. 6.4 shifting slr bit (arcon.5) has to contain the shift direction, and arcon.4 to arcon.0 the shift count (which must not be 0). during shift, zeroes come into the left or right end of the registers md0 or md3, respectively.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 34 - 7. timer 0 and timer 1 the SM39R16A6 has three 16 - bit timer/counter registers: timer 0, timer 1 and timer 2. all can be configured for counter or timer operations. in timer mode, the timer 0 regis ter or timer 1 register is incremented every 1/12/96 machine cycles, which means that it counts up after every 1/12/96 periods of the clk signal. it?s dependent on sfr(pfcon). in counter mode, the register is incremented when the falling edge is observed a t the corresponding input pin t0 or t1. since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for ti mer 0 and timer 1. two special f unction registers (tmod and tcon) are used to select the appropriate mode. mnemonic description dir. bit 7 bit 6 bi t 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst timer 0 and 1 tl0 timer 0 , low byte 8ah tl0[7:0] 00h th0 timer 0 , high byte 8ch th0[7:0] 00h tl1 timer 1 , low byte 8bh tl1[7:0] 00h th1 timer 1 , high byte 8dh th1[7:0] 00h tmod timer mode control 89h gate c/t m1 m0 gate c/t m1 m0 00h tcon timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h pfcon peripheral frequency control register d9h - - srelps[1:0] t1ps[1:0] t0ps[1:0] 00h 7.1 timer/ c ounter mode control register (tmod) mnemonic: tmod address: 89h 7 6 5 4 3 2 1 0 reset gate c/t m1 m0 gate c/t m1 m0 00h timer 1 timer 0 gate: if set, enables external gate control (pin int0 or int1 for counter 0 or 1, respectively). when int0 or int1 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge on t0 or t1 input pin . c/t: selects timer or counter operation. when set to 1, a counter operation is performed, when cleared to 0, the corresponding register will function as a timer.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 35 - m1 m0 mode function 0 0 mode0 1 3 - bit counter/timer, with 5 lower bits in tl0 or tl1 register and 8 bits in th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are hold at zero. 0 1 mode1 16 - bit counter/timer. 1 0 mode2 8 - bit auto - reload co unter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented every machine cycle. when tlx overflows, a value from thx is copied to tlx. 1 1 mode3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independent 8 bit timers / counters. 7.2 timer/counter control register (tcon) mnemonic: tcon address: 88h 7 6 5 4 3 2 1 0 reset tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tf1: timer 1 overflow flag set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr1: timer 1 run control bit. if cleared, timer 1 stops. tf0: timer 0 overflow flag set by hardware when timer 0 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr0: timer 0 run control bit. if cleared, timer 0 stops. ie1: interrupt 1 edge flag. set by hardware, when falling edge on external pin int1 is observed. cleared when interrupt is pro cessed. it1: interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. it1=1, interrupt 1 select falling edge trigger. it1=0, interrupt1 select low level trigger. ie0: interrupt 0 edge flag. set by hardware, when fa lling edge on external pin int0 is observed. cleared when interrupt is processed. it0: interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. it0=1, interrupt 0 select falling edge trigger. it0=0, interrupt 0 sele ct low level trigger.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 36 - 7.3 enhance interrupt trigger sfr(enhit) mnemonic : enhit address : e5h 7 6 5 4 3 2 1 0 reset - enhit1 - enhit0 - - - - 07h note : it is supported the version d of mcu after. enhit1 : interrupt 1 edge trigger control bit. when enhit1 is set to 0 and it1 is set to 1 , the method of edge trigger is falling edge trigger. when enhit1 and it1 both are set to 1 , the method of edge trigger is rising edge trigger. enhit 1 =0 enhit 1 =1 it 1 =0 int 1 low level trigger in t 1 low level trigger it 1 =1 int 1 failing edge trigger int 1 rising edge trigger enhit0 : interrupt 0 edge trigger control bit. when enhit 0 is set to 0 and it 0 is set to 1 , the method of edge trigger is falling edge trigger. when enhit 0 and it 0 both are set to 1 , the method of edge tr igger is rising edge trigger. enhit0=0 enhit0=1 it0=0 int0 low level trigger in t 0 low level trigger it0=1 int0 failing edge trigger int0 rising edge trigger 7.4 peripheral frequency control register mnemonic: pfcon address: d9h 7 6 5 4 3 2 1 0 reset - - srelps[1:0] t1ps[1:0] t0ps[1:0] 00h t 1 ps[1:0] : timer 1 prescaler select t0ps[1:0] prescaler 00 fosc/12 01 fosc 10 fosc/96 11 reserved t0ps[1:0] : timer0 prescaler select
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 37 - t0ps[1:0] prescaler 00 fosc/12 01 fosc 10 fosc/96 11 reserved 7.5 mo de 0 (13 - bit counter/timer) fig. 7 - 1 : mode 0 - 13 bit timer / c ounter operation 12 osc t 1 pin c / t = 0 c / t = 1 00 01 10 t 1 ps [ 1 : 0 ] tl 1 ( 5 bits ) th 1 ( 8 bits ) tf 1 gate 1 int 1 pin not or and tr 1 0 1 0 1 et 1 ea control if not higher priority interrupt processing jump 001 bh d 0 d 1 d 2 d3 d4 d 5 d 6 d7 d0 d1 d 2 d 3 d4 d5 d6 d 7 tf 1 tl 1 th 1 96
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 38 - 7.6 mode 1 (16 - bit counter/timer) fig. 7 - 2 : mode 1 16 bit counter/timer operation 7.7 m ode 2 (8 - bit auto - reload counter/timer) fig. 7 - 3 : mode 2 8 - bit auto - reload counter/timer operation. t 1 pin c / t = 0 c / t = 1 t 1 ps [ 1 : 0 ] tl 1 ( 8 bits ) th 1 ( 8 bits ) tf 1 gate 1 int 1 pin not or and tr 1 0 1 0 1 et 1 ea auto reload 12 osc 00 01 10 96 control if not higher priority interrupt processing jump 001 bh 12 osc t 1 pin c / t = 0 c / t = 1 00 01 10 t 1 ps [ 1 : 0 ] tl 1 ( 8 bits ) th 1 ( 8 bits ) tf 1 gate 1 int 1 pin not or and tr 1 0 1 0 1 et 1 ea control if not higher priority interrupt processing jump 001 bh 96 d 0 d1 d2 d3 d 4 d 5 d 6 d7 tf 1 tl 1 th 1 d 0 d1 d2 d3 d 4 d 5 d 6 d7
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 39 - 7.8 mode 3 (timer 0 acts as two independent 8 bit timers / counters) t0 pin c/t = 0 c/t = 1 t0ps[1:0] tl0 (8 bits) tf0 gate0 /int0 pin not or and tr0 tr1 th0 (8 bits) tf1 interrupt request (001bh) 12 osc 00 01 10 96 control interrupt request (000bh) : ode tmer 0 ats as to ndependent t tmers / counters operatn
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 40 - 8. timer 2 and capture compare unit timer 2 is not only a 16 - bit timer, also a 4 - channel unit with compare, capture and reload functio ns. it is very similar to the programmable counter array (pca) in some other mcus except pulse width modulation (pwm). mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst timer 2 and capture compare unit aux auxiliary register 91h brgs p21cc - p1ur - - - dps 00h t2con timer 2 control c8h t2ps[2:0] t2r[1:0] - t2i[1:0] 00h cccon compare/capture control c9h cci3 cci2 cci1 cci0 ccf3 ccf2 ccf1 ccf0 00h ccen compare/capture enable register c1h - cocam1[2:0] - cocam0[2:0] 00h ccen 2 compare/capture enable 2 register d1h - cocam3[2:0] - cocam2[2:0] 00h tl2 timer 2, low byte cch tl2[7:0] 00h th2 timer 2, high byte cdh th2[7:0] 00h crcl compare/reload/ capture register, low byte cah crcl[7:0] 00h crch compare/reload/ capture regist er, high byte cbh crch[7:0] 00h ccl1 compare/capture register 1, low byte c2h ccl1[7:0] 00h cch1 compare/capture register 1, high byte c3h cch1[7:0] 00h ccl2 compare/capture register 2, low byte c4h ccl2[7:0] 00h cch2 compare/capture register 2, high b yte c5h cch2[7:0] 00h ccl3 compare/capture register 3, low byte c6h ccl3[7:0] 00h cch3 compare/capture register 3, high byte c7h cch3[7:0] 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs p21cc - p1ur - - - dps 00h p 21cc : p 21 cc = 0 ? ca pture/compare function on p1. p 21 cc = 1 ? capture/compare function on p 2 . mnemonic: t2con address: c8h 7 6 5 4 3 2 1 0 reset t2ps[2:0] t2r[1:0] - t2i[1:0] 00h t2ps[2:0]: prescaler select bit: t2ps = 000 ? timer 2 is clocked with the oscillator freque nc y. t2ps = 001 ? timer 2 is clocked with 1/2 of the oscillator frequency. t2ps = 010 ? timer 2 is clocked with 1/4 of the oscillator frequency. t2ps = 011 ? timer 2 is clocked with 1/6 of the oscillator frequency.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 41 - t2ps = 100 ? timer 2 is clocked with 1/8 of the oscillator frequency. t2ps = 101 ? timer 2 is clocked with 1/12 of the oscillator frequency. t2ps = 110 ? timer 2 is clocked with 1/24 of the oscillator frequency. t2r[1:0]: timer 2 reload mode selection t2r[1:0] = 0x ? reload disabled . t2r[1:0] = 10 ? mode 0: auto reload . t2r[1:0] = 11 ? mode 1: t2ex falling edge reload . t2i[1:0]: timer 2 input selection t2i[1:0] = 00 ? timer 2 stop . t2i[1:0] = 01 ? input frequency from prescaler (t2ps[2:0]) . t2i[1:0] = 10 ? timer 2 is incremented by external sign al at pin t2 . t2i[1:0] = 11 ? internal clock input is gated to the timer 2 . mnemonic: cccon address: c9h 7 6 5 4 3 2 1 0 reset cci3 cci2 cci1 cci0 ccf3 ccf2 ccf1 ccf0 00h cci3: compare/capture 3 interrupt control bit. cci3 = 1 is enable. cci2: compa re/c apture 2 interrupt control bit. cci3 = 1 is enable. cci1: compare/capture 1 interrupt control bit. cci3 = 1 is enable. cci0: compare/c apture 0 interrupt control bit. cci3 = 1 is enable. ccf3: compare/capture 3 flag set by hardware. this flag can be cleared by software. ccf2: compare/capture 2 flag set by hardware. this flag can be cleared by software. ccf1: compare/capture 1 flag set by hardware. this flag can be cleared by software. ccf0: compare/capture 0 flag set by hardware. this flag can be c leared by software. compare/capture interrupt share t2 interrupt vector. mnemonic: ccen address: c1h 7 6 5 4 3 2 1 0 reset - cocam1[2:0] - cocam0[2:0] 00h cocam1[2:0] 000 - compare/capture disable . 001 - compare enable but no output on pin . 010 - compare mode 0 . 011 - compare mode 1 . 100 - capture on rising edge at pin cc1 .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 42 - 101 - capture on falling edge at pin cc1 . 110 - capture on both rising and falling edge at pin cc1 . 111 - capture on write operation into register cc1 . cocam0[2:0] 000 - com pare/capture disable . 001 - compare enable but no output on pin . 010 - compare mode 0 . 011 - compare mode 1 . 100 - capture on rising edge at pin cc0 . 101 - capture on falling edge at pin cc0 . 110 - capture on both rising and falling edge at pin cc0 . 111 - capture on write operation into register cc0 . mnemonic: ccen2 address: d1h 7 6 5 4 3 2 1 0 reset - cocam3[2:0] - cocam2[2:0] 00h cocam3[2:0] 000 - compare/capture disable . 001 - compare enable but no output on pin . 010 - compare mode 0 . 011 - comp are mode 1 . 100 - capture on rising edge at pin cc3 . 101 - capture on falling edge at pin cc3 . 110 - capture on both rising and falling edge at pin cc3 . 111 - capture on write operation into register cc3 . cocam2[2:0] 000 - compare/capture disable . 001 - compare enable but no output on pin . 010 - compare mode 0 . 011 - compare mode 1 . 100 - capture on rising edge at pin cc2 . 101 - capture on falling edge at pin cc2 . 110 - capture on both rising and falling edge at pin cc2 . 111 - capture on write operation i nto register cc2 .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 43 - 8.1 timer 2 function timer 2 can operate as timer, event counter, or gated timer as explained later. 8.1.1 timer mode in this mode timer 2 can by incremented in various frequency that depending on the prescaler. the prescaler is selected b y bit t2ps[2:0] in register t2con. a s shown in fig. 8 - 1 fig. 8 - 1 : timer mode and reload mode function 8.1.2 event counter mode in this mode, the timer is incremented when external signa l t2 change value from 1 to 0. the t2 input is sampled in every cycle. timer 2 is incremented in the cycle following the one in which the transition was detected. as shown in fig. 8 - 2 . fig. 8 - 2 : event counter mode function 8.1.3 gated timer mode in th is mode, the internal clock which incremented timer 2 is gated by external signal t2. as shown in fig. 8 - 3
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 44 - fig. 8 - 3 : gated timer mode function 8.1.4 reload of timer 2 reload (16 - bit reload from the crc register) ca n be executed in the following two modes: mode 0: reload signal is generat e by a timer 2 overflows ? auto reload . mode 1: reload signal is generate by a negative transition at the corresponding input pin t2ex.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 45 - 8.2 compare function in the four independent comp arators, the value stored in any compare/capture register is compared with the contents of the timer register. the compare modes 0 an d 1 are selected by bits c0camx . in both compare modes, the results of comparison arrives at port 1 within the same machin e cycle in which the internal compare signal is activated. 8.2.1 compare mode 0 in mode 0, when the value in timer 2 equals the value of the compare register, the output signal changes from low to high. it goes back to a low level on timer overflow. in this mo de, writing to the port will have no effect, because the input line from the internal bus and the write - to - latch line are disconnected. as shown in fig. 8 - 4 illustrates the function of compare mode 0. crc or ccx contents of timer 2 reload value ccx output timer 2 = ccx value timer 2 overflow fig. 8 - 4 : compare mode 0 function 8.2.2 compare mode 1 in compare mode 1, the transition of the output signal can be determined by software. a timer 2 ov erflow causes no output change. in this mode, both transitions of a sig nal can be contr olled. as show n in fig. 8 - 5 and fig. 8 - 6 a functional diagram of a register/port configuration in compare mode 1. in compare mode 1, the value is written first to the ?sha dow register?, when compare signal is active, this value is transferred to the output register. fig. 8 - 5 : mode 1 r egister/ p ort function
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 46 - crc or ccx contents of timer 2 reload value ccx output timer 2 = ccx value ccx shadow register timer 2 = ccx value fig. 8 - 6 : compare mode 1 function
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 47 - 8.3 capture function actual timer/counter contents can be saved into registers ccx or crc upon an external event (mode 0) or a software write operation (mode 1). 8.3.1 capture mode 0 (by hardware) in mode 0, value capture of timer 2 is executed whe n: (1) rising edge on input cc0 - cc3 (2) falling edge on input cc0 - cc3 (3) both rising and falling edge on input cc0 - cc3 the contents of timer 2 will be latched into the appropriate capture register. a s shown in fig. 8 - 7 fig. 8 - 7 : capture mode 0 function 8.3.2 capture mode 1(by software) in mode 1, value capture of timer 2 is caused by writing any value into the low - order byte of the dedicated capture register. the value written to the capture register is irrelevant to this func tion. the contents of timer 2 will be latched into the appropriate capture register. a s shown in fig. 8 - 8 fig. 8 - 8 : capture mode 1 function
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 48 - 9. serial interface the serial buffer consists of two separate register s, a t ransmit buffer and a receive buffer. writing data to the special function register sbuf sets this data in serial output buffer and starts the transmission . reading from the sbuf reads data from the serial receive buffer. the serial port can simultan eously transmit and receive data. it can also buffer 1 byte at receive, which prevents the receive data from being lost if the cpu reads the first byte before transmission of the second byte is completed. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst serial interface pcon power control 87h sm od mduf - - - - stop idle 4 0h aux auxiliary register 91h brgs p21c c - p1ur - - - dps 00h scon serial port control register 98h sm 0 sm 1 sm 2 ren tb8 rb8 ti ri 00h srell serial port re load register low byte aah srel. 7 srel. 6 srel. 5 srel. 4 srel. 3 srel. 2 srel. 1 srel. 0 00h srelh serial port reload register high byte bah - - - - - - srel. 9 srel. 8 00h sbuf serial port data buffer 99h sbuf[7:0] 00h pfcon peripheral frequency control regist er d9h - - srelps[1:0] t1ps[1:0] t0ps[1:0] 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs p21cc p1ur - - dps 00h brgs: baud rate generator. brgs = 0 - baud rate generator from timer 1. brgs = 1 - baud rate generator by srel. p 1 ur: p 1 ur = 0 - serial interface function on p 3 . p 1 ur = 1 - serial interface function on p 1 . mnemonic: scon address: 98h 7 6 5 4 3 2 1 0 reset sm 0 sm 1 sm 2 ren tb8 rb8 ti ri 00h sm 0, sm 1: serial port 0 mode selection. sm 0 sm 1 mode 0 0 0 0 1 1 1 0 2 1 1 3 the 4 modes in uart, mode 0 ~ 3, are explained later. sm 2: enables multi processor communication feature . ren: if set, enables serial reception. cleared by software to disable reception. tb8: the 9 th tran sm itted data bit in modes 2 and 3. set or cleared by the cpu depending on
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 49 - the function it performs such as parity check, multiprocessor communication etc. rb8: in modes 2 and 3, it is the 9 th data bit received. in mode 1, if sm 2 is 0, rb8 is the stop bit. in mode 0, this bit is not used. must be cleared by software. ti: tran sm it interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software. ri: receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. 9.1 serial interfa ce the serial interface can operate in the following 4 modes: sm 0 sm 1 mode description board rate 0 0 0 shift register fosc/12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fosc/32 or fosc/64 1 1 3 9 - bit uart variable here fosc is the crystal or oscilla tor frequency. 9.1.1 mode 0 pin rxd serves as input and output. txd outputs the shift clock. 8 bits are tran sm itted with lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in mode 0 by setting the flags in scon as follow s: ri = 0 and ren = 1. in other modes, a start bit when ren = 1 starts receiving serial data. a s shown in fig. 9 - 1 and fig. 9 - 2 fig. 9 - 1 : tran sm it mode 0 fig. 9 - 2 : receive mode 0
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 50 - 9.1.2 mode 1 pin rxd serves as input, and txd serves as serial output. no external shift clock is used, 10 bits are tran sm itted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the tran sm ission, 8 data bits are available by reading sbuf, and stop bit sets the flag rb8 in the special function register scon. in mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate. a s shown in fig. 9 - 3 and fig. 9 - 4 fig. 9 - 3 : transmit mode 1 fig. 9 - 4 : receive mode 1 9.1.3 mo de 2 this mode is similar to mode 1, with two differences. the baud rate is fixed at 1/32 ( smod =1) or 1/64( smod =0) of oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable 9 th bit, and a stop bit (1). the 9 th bit can be used to control the parity of the serial interface: at transmission , bit tb8 in scon is output as the 9 th bit, and at receive, the 9 th bit affects rb8 in special function register scon. 9.1.4 mode 3 the only difference between mode 2 and mode 3 is that in mode 3 either internal baud rate generator or timer 1 can be use to specify baud rate. a s shown in fig. 9 - 5 and fig. 9 - 6 . fig. 9 - 5 : transmit modes 2 and 3
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 51 - fig. 9 - 6 : receive modes 2 and 3 9.2 multiprocessor communication of serial interface the feature of receiving 9 bits in modes 2 and 3 of serial interface can be used for multiprocessor co mmunication. in this case, the slave processors have bit sm 2 in scon set to 1. when the master processor outputs slave?s address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. the slave processors compare the received byte with their network address. if there is a match, the addressed slave will clear sm 2 and receive the rest of the message, while other slaves will leave sm 2 bit unaffected and ignore this message. after addressing the slave, the host will output the re st of the message with the 9 th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves. 9.3 peripheral frequency control register mnemonic: pfcon address: d9h 7 6 5 4 3 2 1 0 reset - - srelps[1:0] t1ps[1:0] t0ps[1:0] 00h s relps[1:0]: srel prescaler select srelps[1:0] prescaler 00 fosc/64 01 fosc /32 t1ps[1:0]: timer1 prescaler select t1ps[1:0] prescaler 00 fosc/12 01 fosc 10 fosc/96 11 reserved
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 52 - 9.4 baud rate generator 9.4.1 serial interface modes 1 and 3 9.4.1.1 when brgs = 0 (in special function register aux). (1) t1ps[1:0] is 00 ( ) th1 256 12 32 f 2 rate baud osc smod ? = ( ) th1 256 32 f 2 rate baud osc smod ? = ( ) th1 256 96 32 f 2 rate baud osc smod ? = 9.4.1.2 when brgs = 1 (in special function register aux). (1) srelps[1:0] is 00 ( ) srel 2 64 f 2 rate baud 10 osc smod ? = ( ) srel 2 32 f 2 rate baud 10 osc smod ? =
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 53 - 10. watchdog timer the watch dog timer (wdt) is an 8 - bit free - running counter that generate reset signal if the counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or ele ctronics discharge which causing software dead loop or runaway. the wdt function can help user software recover from abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by sof tware periodically clearing the wdt counter. user should check wdtf bit of wdtc register whenever un - predicted reset happened. after an external reset the watchdog timer is disabled and all registers are set to zeros. the watchdog timer has a free r unning on- chip rc oscillator (2 3 khz) . the wdt will keep on running even after the system clock has been turned off (for example, in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the mcu to reset. the wdt can be enabl ed or disabled any time during the normal mode. please refer the wdte bit of wdtc register. the default wdt time - o ut period is approximately 1 78.0 ms (wdtm [3:0] = 0100b). the wdt has selectable divider input for the time base source clock. to select the di vider input, the setting of bit3 ~ bit0 (wdtm [3:0]) of watch dog timer control register (wdtc) should be set accordingly . as shown in table 10 - 1 . wdtm 2 23khz = wdtclk watchdog reset time = wdtclk 256 table 10- 1 : wdt time - out period wdtm [3:0] divider (2 3 khz rc oscillator in) time period @ 2 3 khz 0000 1 1 1.1 ms 0001 2 22.2 ms 0010 4 44.5 ms 0011 8 89. 0 ms 0100 16 178.0 ms (default) 0101 32 356.1 ms 0110 64 712.3 ms 0111 128 1. 4246 s 1000 256 2.8493 s 1001 512 5.6987 s 1010 1024 11.397 s 1011 2048 22.795 s 1100 4096 45.590 s 1101 8192 91.180 s 1110 16384 182.36 s 1111 32768 364.72 s note: rc oscillator ( 23 khz ), about 20% of varia tion when mcu is reset, the mcu wil l be read wdten control bit status. when wdten bit is set to 1, the watchdog function will be disabled no matter what the wdte bit status is. when wdten bit is clear to 0, the watchdog function will be enabled if wdte bit is set to 1 by program. user can t o set wdten on the writer or isp. the program can enable the wdt function by programming 1 to the wdte bit premise that wdten control bit is clear to 0. after wdte set to 1, the 8 bit - counter starts to count with the selected time base source clock which s et by wdtm [3:0]. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when mcu been reset, either hardware reset or wdt reset . as shown in fig. 10 - 1 .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 54 - once the watchdog is started it cann ot be stopped. user can refreshed the watchdog timer to zero by writing 0x55 to watch dog timer refresh key (wdtk) register. this will clear the content of the 8 - bit counter and let the counter re - start to count from the beginning. the watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. when watchdog timer is overflow, the wdtf flag will set to one and automatically reset mcu. the wdtf flag can be clear by software or external reset or power on reset. 23khz rc oscillator wdtm 2 1 wdtc takey (55, aa, 5a) wdtm[3:0] wdten enable/disable wdt wdt counter wdtclk wdtk (0x55) refresh wdt counter 1. power on reset 2. external reset 3. software write ?0? wdtf set wdtf = 1 clear wdtf = 0 wdt time-out reset enable wdtc write attribute wdt time-out select wdt time-out interrupt cwdtr = 0 cwdtr = 1 fig. 10 - 1 : watchdog timer block diagram mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst watchdog timer takey time access key register f7h takey [7:0] 00h w dtc watchdog timer control register b6h - cwdtr wdte - wdtm [3:0] 04h wdtk watchdog timer refresh key b7h wdtk[7:0] 00h rsts reset status register a1h - lvrlp intf lvrlp f pdrf wdtf swrf lvrf porf 00h mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h watchdog timer control register (wdtc) is read - only by default; software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the wdtc write attribute. that is: mov takey, #55h mov takey, #0aah mov takey, #5ah
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 55 - mnemonic: wdtc address: b6h 7 6 5 4 3 2 1 0 reset - cwdtr wdte - wdtm [3:0] 04h cwdtr: watch dog states select bit(support stop mode wakeup) cwdtr = 0 - enable watch dog reset. cwdtr = 1 - enable watch dog interrup t. wdte: control bit used to enable watchdog timer. the wdte bit can be used only if wdten is "0". if the wdten bit is "0", then wdt can be disabled / enabled by the wdte bit. wdte = 0 - disable wdt. wdte = 1 - enable wdt. the wdte bit is not used if wdten is "1". that is, if the wdten bit is "1" , wdt is always disabled no matter what the wdte bit status is. the wdte bit can be read and written. wdtm [3:0]: wdt clock sour ce divider bit. as seen in fig. 10- 1 to reference the wdt time - out period. mnemonic: rsts address: a 1h 7 6 5 4 3 2 1 0 reset - lvrlp intf lvrlp f pdr f wdtf swrf lvrf porf 00h wdtf: watchdog timer reset flag. when mcu is reset by watchdog, wdtf flag will be set to one by hardware. this flag clear by software mnemonic: wdtk address: b7h 7 6 5 4 3 2 1 0 reset wdtk[7:0] 00h wdtk: watchdog timer refresh key. a programmer must write 0x55 into wdtk register, and then the watchdog timer will be cleared to zero. for example 1, if enable wdt and select time - out reset period is 2.8493 s. first, programming the information block op3 bit7 wdten to ?0?. secondly, mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable wdtc write attribute. mov wdtc, #28h ; set wdtm [3:0] = 1000b. set wdte =1 to enable wdt function. . . . mov wdtk, #55h ; clear wdt timer to 0.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 56 - for example 2, if enable wdt and select tim e - out interrupt period is 178.0m s. first, programming the information block op3 bit7 wdten to ?0?. secondly, mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable wdtc write attribute. mov wdtc, #64h ; set wdtm [3:0] = 01 00b . ;set wdte =1 to enable wdt function ; and set cwdtr =1 to enable period interrupt function
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 57 - 11. interrupt the SM39R16A6 provides 1 2 interrupt sources with four priority levels. each sour ce has its own request flag(s) located in a special function register. each interrupt requested by the corresponding flag could individually be enabled or disabled by the enabl e bits in sfr?s ien0, ien1 . when the interrupt occurs, the engine will vector to the predetermined address as given in table 11 - 1 . once interrupt service has begun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminated by a return from instruction reti. when an reti is performed, the processor will return to the instruction that would have been next when interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by setting a flag bit. this bit is set regardless of whether the interrup t is enabled or disabled. each interrupt flag is sampled once per machine cycle, and then samples are polled by hardware. if the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is set. on the next instruction cycle the interrupt will be acknowledged by hardware forcing an lcall to appropriate vector address. interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt occurs. if microcontroller is perfor ming an interrupt service with equal or greater priority, the new interrupt will not be invoked. in other cases, the response time depends on current instruction. the fastest possible response to an interrupt is 7 machine cycles. this includes one machine cycle for detecting the interrupt and six cycles for perform the lcall. table 11 - 1 : interrupt vectors interrupt request flags interrupt vector address interrupt number *(use keil c tool) 1 ie0 ? external interrupt 0 0003h 0 2 tf0 ? timer 0 interrupt 000bh 1 3 ie1 ? external interrupt 1 0013h 2 4 tf1 ? timer 1 interrupt 001bh 3 5 ri /ti ? serial channel interrupt 0023h 4 6 tf2/exf2 ? timer 2 interrupt 002bh 5 7 pwmif ? pwm interrupt 0043h 8 8 spi if ? spi interrupt 004bh 9 9 adcif ? a/d converter interrupt 0053h 10 1 0 lviif ? low voltage interrupt 0063h 12 1 1 iicif ? iic interrupt 006bh 13 1 2 wdt ? watchdog interrupt 008bh 17 *see keil c about c51 user?s guide about interrupt function descri ption
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 58 - mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst interrupt ien0 interrupt enable 0 register a8h ea - et2 es et1 ex1 et0 ex0 00h ien1 interrupt enable 1 register b8h exe n 2 - ieiic ielvi - ieadc iespi - 00h ien2 inter rupt enable 2 register 9ah - - - - - - ewdt - 00h ircon interrupt request register c0h exf2 tf2 iicif lviif - adcif spiif - 00h ircon2 interrupt request register 2 97h - - - - - - wdtif - 00h ip0 interrupt priority level 0 a9h - - ip0.5 ip0.4 ip0.3 ip0. 2 ip0.1 ip0.0 00h ip1 interrupt priority level 1 b9h - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h mnemonic: ien0 address: a8h 7 6 5 4 3 2 1 0 reset ea - et2 es et1 ex1 et0 ex0 00h ea: ea=0 ? disable all interrupt. ea=1 ? enable all interrupt. et2: e t2=0 ? disable timer 2 overflow or external reload interrupt. et2=1 ? enable timer 2 overflow or external reload interrupt. es: es=0 ? disable serial channel interrupt. es=1 ? enable serial channel interrupt. et1: et1=0 ? disable timer 1 overflow interru pt. et1=1 ? enable timer 1 overflow interrupt. ex1: ex1=0 ? disable external interrupt 1. ex1=1 ? enable external interrupt 1. et0: et0=0 ? disable timer 0 overflow interrupt. et0=1 ? enable timer 0 overflow interrupt. ex0: ex0=0 ? disable external inte rrupt 0. ex0=1 ? enable external interrupt 0. mnemonic: ien1 address: b8h 7 6 5 4 3 2 1 0 reset exen2 - ieiic ielvi - ieadc iespi - 00h exen2: timer 2 reload interrupt enable. exen2 = 0 ? disable timer 2 external reload interrupt. exen2 = 1 ? enable timer 2 external reload interrupt. ieiic: iic interrupt enable. ieiics = 0 ? disable iic interrupt.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 59 - ieiics = 1 ? enable iic interrupt. ielvi: lvi interrupt enable. ielvi = 0 ? disable lvi interrupt. ielvi = 1 ? enable lvi interrupt. ieadc: a/d converter interrupt enable ieadc = 0 ? disable adc interrupt. ieadc = 1 ? enable adc interrupt. iespi: spi interrupt enable. iespi = 0 ? disable spi interrupt. iespi = 1 ? enable spi interrupt. mnemonic: ien2 address: 9ah 7 6 5 4 3 2 1 0 reset - - - - - - ewdt - 00h ewdt : enable watch dog interrupt. ewdt = 0 ? disable watch dog interrupt. ewdt = 1 ? enable watch dog interrupt. mnemonic: ircon address: c0h 7 6 5 4 3 2 1 0 reset exf2 tf2 iicif lviif - adcif spiif - 00h exf2: timer 2 external reload flag. must be cleared by software. tf2: timer 2 overflow flag. must be cleared by software. iicif: iic interrupt flag. hardware will clear this flag automatically when enter interrupt vector. lviif: lvi interrupt flag. hardware will clear this flag automatica lly when enter interrupt vector. adcif: a/d converter end interrupt flag. hardware will clear this flag automatically when enter interrupt vector. spiif: spi interrupt flag. hardware will clear this flag automatically when enter interrupt vector. mnemo nic:ircon2 address: 97h 7 6 5 4 3 2 1 0 reset - - - - - - wdtif - 00h wdtif: watch dog interrupt flag . hardware will clear this flag automatically when enter interrupt vector.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 60 - 11.1 priority level structure all interrupt sources are combined in group s , as given in table 11 - 2 . table 11 - 2 : priority level groups groups external interrupt 0 - pwm interrupt timer 0 interrupt watchdog interrupt spi interrupt external interrupt 1 - adc interrupt timer 1 interrupt - - serial channel interrupt - lvi interrupt timer 2 interrupt - iic interrupt each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the s pecial function register ip 0 and one in ip 1. if requests of the same priority level will be received simultaneously, an internal polling sequence determines which request is serviced first. as given in table 11 - 3 and table 11 - 4 and table 11 - 5 . mnemonic: ip0 address: a9h 7 6 5 4 3 2 1 0 reset - - ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 00h mnemonic: ip1 address: b9h 7 6 5 4 3 2 1 0 reset - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 0 0h table 11 - 3 : priority levels ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 11 - 4 : groups of priority bi t group ip1.0, ip0.0 external interrupt 0 - pwm interrupt ip1.1, ip0.1 timer 0 interrupt watchdog interrupt spi interrupt ip1.2, ip0.2 external interrupt 1 - adc interrupt ip1.3, ip0.3 timer 1 interrupt - - ip1.4, ip0.4 serial channel interrupt - lvi interrupt ip1.5, ip0.5 timer 2 interrupt - iic interrupt
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 61 - table 11 - 5 : polling sequence interrupt source sequence external interrupt 0 pwm interrupt timer 0 interrupt watchdog interrupt spi interrupt external interrupt 1 adc interrupt timer 1 interrupt serial channel interrupt lvi interrupt timer 2 interrupt iic interrupt polling sequence
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 62 - 12. power management unit power management unit serves two power management modes, idle and stop, for th e users to do power saving function. mnemonic: pcon address: 87h 7 6 5 4 3 2 1 0 reset sm od mduf - - - - stop idle 4 0h stop: stop mode control bit. setting this bit turning on the stop mode. stop bit is always read as 0 idle: idle mode control bit. setting this bit turning on the idle mode. idle bit is always read as 0 12.1 idle mode setting the idle bit of pcon register invokes the idle mode. the idle mode leaves internal clocks and peripherals running. power consumption drops because the cpu is not act ive. the cpu can exit the idle state with any interrupts or a reset. 12.2 stop mode setting the stop bit of pcon register invokes the stop mode. all internal clocking in this mode is turn off. the cpu will exit this state from a no - clocked interrupt (external i n t0/1 , lvi and watchdog interrupt) or a reset (wdt and lvr) condition. internally generated interrupts (timer, serial port ...) have no effect on stop mode since they require clocking activity.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 63 - 13. pulse width modulation (pwm) pwm module features : ? four - chan nel ( tow - pair) pwm output pins. ? 14- bit resolution. the interrupt vector is 43h. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst pwm pwmtbc0 pwm time base control 0 reg. f9 h - - - - pwmtbpre [1:0] pwmtbmod [1:0] 00h pwmtbc 1 pwm time base control 1 reg. fa h pwm tben - - pwm protec tdis - - - pwmp ie 10h pwmop mod pwm output pair mode reg. fb h - - - - pwm op3 mod pwmo p2 mod - - 00h periodl pwm period (low) reg. f1 h pwm period low 8 bit ffh periodh pwm period ( high) reg. f 2 h - - pwm period high 6 bit 3fh pwmen pwm output enable reg. f5 h pwm7 en pwm6 en pwm5 en pwm4 en - - - - 00h pwmtb post scale pwm t ime base post scale reg. ee h pwmtbpost[7:0] 00h pwmintf pwm int flag reg. bch pwm tbdir - - - - - - pwmp if 00h pwmpola rit y pwm polarity reg. ddh polarity 7 polarity 6 polarity 5 polarity 4 - - - - ffh duty2l pwm 2 duty low byte reg. d5 h pwm2 duty low 8 bit 00h duty2h pwm 2 duty high byte reg. d6 h - - pwm2 duty high 6 bit 00h duty3l pwm 3 duty low byte reg. d7 h pwm3 duty low 8 bit 00h duty3h pwm 3 duty high byte reg. c9 h - - pwm3 duty high 6 bit 00h
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 64 - mnemonic: pwmtbc0 (pwm time base control 0) address: f9 h 7 6 5 4 3 2 1 0 reset - - - - pwmtbpre[1:0] pwmtbmod[1:0] 00h pwmtbpre [1:0] : pwm time base prescale . pwm tbpr e [ 1 :0] mode 00 fosc 01 fosc/4 10 fosc/16 11 fosc/64 pwm tbmod : pwm time base mode . pwmtbmod [1:0] = 00 - free running mode ( edge - align ). pwmtbmod [1:0] = 01 - s ingle - shot mode ( edge - align ). pwmtbmod [1:0] = 10 - c ontinuous up/down counting mode (c enter - align ) . ( tbcounter = period g enerate an interrupt ) pwmtbmod [1:0] = 11 - c ontinuous up/down counting with i nterrupt for double pwm updates (c enter - align ) . ( tbcounter = period and tbcounter = 0 g enerate an interrupt ) freq = 24mhz, period = 14 bit prescale pwm frequency edge - align pwm frequency c enter - align 1:1 1500 hz 750 hz 1:4 375 hz 188 hz 1:16 94 hz 47 hz 1:64 23 hz 12 hz mnemonic: pwmtbc1 (pwm time base control 1) address: fa h 7 6 5 4 3 2 1 0 reset pwmtb en - - pwmpro tec tdis - - - pwmpie 10h pwm tben : pwm time base enable 0 = pwm time base disable . 1 = pwm time base enable . wmprotectdis: pwm protect set (fool proof circuit) 0 = enable . (aaply to complementary mode ) 1 = disable . pwm4/pwm5, pwm6/pwm7, protect enable/ disable. pwmpie: pwm period interrupt enable pwmpie = 0 - pwm period interrupt diable . pwmpie = 1 - pwm period interrupt enable .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 65 - fig. 13 - 1 : opertion of the pwm protect mode mnemonic: pwmop m od (pwm o utput pair mode) address: fb h 7 6 5 4 3 2 1 0 reset - - - - pwmop3 mod pwmop2 mod - - 00h pwmop3mod : pwm output pair 3 mode . 0 = (pwm6, pwm7) is complementary mode . 1 = (pwm6, pwm7) is independent mode . pwmop2mod : pwm output pair 2 mode . 0 = (pwm4, pwm5 ) is complementary mode . 1 = (pwm4, pwm5) is independent mode . mnemonic: pwmen address: f5 h 7 6 5 4 3 2 1 0 reset pwm7en pwm6en pwm5en pwm4en - - - - 00h pwm 7en : pwm 7 enable . pwm7en = 0 - pwm 7 output disable . pwm7en = 1 - pwm 7 output enable . p wm 6en : pwm 6 enable . pwm6en = 0 - pwm 6 output disable . pwm6en = 1 - pwm 6 output enable . pwm 5en : pwm 5 enable .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 66 - pwm5en = 0 - pwm 5 output disable . pwm5en = 1 - pwm 5 output enable . pwm 4en : pwm 4 enable . pwm4en = 0 - pwm 4 output disable . pwm4en = 1 - pwm 4 ou tput enable . mnemonic: pwm tbpostscale address: ee h 7 6 5 4 3 2 1 0 reset pwmtbpost [7:0] 00h pwmtbpost [7:0] pwm time base post scale. (how many pwm period happen will a triger need) 0000_0000 = 1: 1 postscale 0000_0001 = 1: 2 postscale : : 0000_1111 = 1: 16 postscale 0001_0000 = 1: 17 postscale : : 1111_1111 = 1: 256 postscale mnemonic: pwmintf (pwm interrupt flag) address: b c h 7 6 5 4 3 2 1 0 reset pwmtb dir - - - - - - pwmp if 00h pwmtbdir : pwm time base count direction status . (read only) 0 = counts up . 1 = counts down . pwmpif : pwm period interrupt flag . must be cleared by software. mnemonic: pwmpolarity address: dd h 7 6 5 4 3 2 1 0 reset polarity 7 polarity 6 polarity 5 polarity 4 - - - - ffh polarity7 : pwm polarity 7 polarity7 = 0 - pwm 7 polarity active low . polarity7 = 1 - pwm 7 polarity active high . polarity6 : pwm polarity 6 polarity 6 = 0 - pwm 6 polarity active low .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 67 - polarity6 = 1 - pwm 6 polarity active high . polarity5 : pwm polar ity 5 polarity5 = 0 - pwm 5 polarity active low . polarity5 = 1 - pwm 5 polarity active high . polarity4 : pwm polarity 4 polarity4 = 0 - pwm 4 polarity active low . polarity4 = 1 - pwm 4 polarity active high .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 68 - 14. iic function the iic module uses the scl (cloc k) and the sda (data) line to communicate with external iic interface. its speed can be selected to 400kbps (maximum) by software setting the iicbr [2:0] control bit. the iic module provided 2 interrupts (rxif, txif). it will generate start, repeated start and stop signals automatically in master mode and can detects start, repeated start and stop signals in slave mode. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pf. the in terrupt vector is 6bh. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst iic function iicctl iic control register f9h iicen mss mas ab_e n bf_en iicbr[2:0] 04h iics iic status register f8h - mpif laif rxif txif rxak txak rw or bb 00h iica1 iic address 1 register fah iica1[7:1] matc h1or rw1 a0h iica2 iic address 2 register fbh iica2[7:1] matc h2 or rw2 60h iicrwd iic read/write register fch iicrwd[7:0] 00h iicebt iic enaable bus transaction fdh fu_en - - - - - - 00h m nemonic: iicctl address: f9h 7 6 5 4 3 2 1 0 reset iicen mss mas ab_en bf_en iicbr[2:0] 04h iicen: enable iic module iicen = 1 is enable . iicen = 0 is disable. mss: master or slave mode select. mss = 1 is master mode. mss = 0 is slave mode. *the softw are must set this bit before setting others register. mas: master address select (master mode only) mas = 0 is to use iica 1. mas = 1 is to use iica2. ab_en: arbitration lost enable bit. (master mode only) if set ab_en bit, the hardware will check arbitra tion lost. once arbitration lost occurred, hardware will return to idle state. if this bit is cleared, hardware will not care arbitration lost condition. set this bit when multi - master and slave connection. clear this bit when single master to single slave . bf_en: bus busy enable bit. (master mode only) if set bf_en bit, hardware will not generate a start condition to bus until bf=0. clear this bit
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 69 - will always generate a start condition to bus when mstart is set. set this bit when multi - master and slave co nnection. clear this bit when single master to single slave. iicbr[2:0]: baud rate selection (master mode only), where fosc is the external crystal or oscillator frequency. the default is fosc/512 for users? convenience. iicbr[2:0] baud rate 000 fosc/3 2 001 fosc/64 010 fosc/128 011 fosc/256 100 fosc/512 101 fosc/1024 110 fosc/2048 111 fosc/4096 mnemonic: iics address: f8h 7 6 5 4 3 2 1 0 reset - mpif laif rxif txif rxak txak rw or bb 00h mpif: the stop condition interrupt flag the stop condition occurred and this bit will be set. software need to clear this bit laif: arbitration lost bit. (master mode only) the arbitration interrupt flag, the bus arbitration lost occurred and this bit will be set. software need to clear this bit rxif: the data receive interrupt flag (rxif) is set after the iicrwd (iic read write data buffer) is loaded with a newly receive data. txif: the data transmit interrupt flag (txif) is set when the data of the iicrwd (iic read write data buffer) is downloaded to the shift register. rxak: the acknowledge status indicate bit. when clear, it means an acknowledge signal has been received after the complete 8 bits data transmit on the bus. txak: the acknowledge status transmit bit. when received complete 8 bits data , this bit will set (noack) or clear (ack) and transmit to master to indicate the receive status. rw or bb: master mode: bb : bus busy bit if detect scl=0 or sda=0 or bus start, this bit will be set. if detect stop,this bit will be cleared. this bit can b e cleared by software to return ready state. slave mode: rw:the slave mode read (received) or wrote ( transmit ) on the iic bus. when this bit is clear, the slave module received data on the iic bus (sda).(slave mode only) . as shown i n fig. 14 - 1
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 70 - fig. 14 - 1 : acknowledgement bit in the 9 th bit of a byte transmission mnemonic: iica 1 address: f a 7 6 5 4 3 2 1 0 reset iica1[7:1] match1 or rw1 a 0h r/w r or r/w slave mode: iica1[7:1]: iic address registers this is the first 7 - bit address for this slave module. it will be checked when an address (from master) is receive d match1: when iica1 matches with the received address from the master side, this bit will set to 1 by hardware. when iic bus gets first data, this bit will clear. master mode: iica1[7:1]: iic address registers this 7 - bit address indicates the slave w ith which it wants to communicate. rw1: this bit will be sent out as rw of the slave side if the module has set the mstart or rstart bit. it appears at the 8 th bit after the i ic address as below figure . it is used to tell the salve the direction of the fo llowing communication. if it is 1, the module is in master receive mode. if 0, the module is in master transmit mode. as shown i n fig. 14- 2 rw1=1, master receive mode rw1=0, master transmit mode fig. 14 - 2 : rw bit in the 8 th bit after iic address
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 71 - mnemonic: iica 2 address: f b 7 6 5 4 3 2 1 0 reset iica 2 [7:1] match 2 or rw 2 6 0h r/w r or r/w slave mode: iica2[7:1]: iic address registers this is the second 7 - bit address for this slave module. it will be checked when an address (from master) is received match2: when iica2 matches with the received address from th e master side, this bit will set to 1 by hardware. when iic bus gets first data, this bit will clear. master mode: iica2[7:1]: iic address registers this 7 - bit address indicates the slave with which it wants to communicate. rw2: this bit will be sent out as rw of the slave side if the module has set the mstart or rstart bit. it is used to tell the salve the direction of the following communication. if it is 1, the module is in master receive mode. if 0, the module is in master transmit mode. rw2=1, ma ster receive mode rw2=0, master transmit mode mnemonic: iicrwd address: fch 7 6 5 4 3 2 1 0 reset iicrwd[7:0] 00h iicrwd[7:0]: iic read write data buffer. in receiving (read) mode, the received byte is stored here. in transmit ting mode, the byte to be shifted out through sda stays here. mnemonic: iicebt address: fdh 7 6 5 4 3 2 1 0 reset f u _ en - - - - - - 00h master mode 00: reserved 01: iic bus module will enable read/write data transfer on sda and scl. 10: iic bus module generate a start condition on the sda/scl, then send out address which is stored in the iica1/iica2(selected by mas control bit) 11: iic bus module generates a stop condition on the sda/scl. fu_en[7:6] will be auto - clear by hardware, so setting fu_en[7:6] repeatedly is necessary. slave mode: 01: fu_en[7:6] should be set as 01 only. the other value is inhibited. notice: fu_en[7:6] shoul d be set as 01 before read/write data transfer for bus release; otherwise,
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 72 - scl will be locked(pull low). fu_en[7:6] should be set as 01 after read/write data transfer for receiving a stop condition from bus master. in transmit data mode (slave mode), the o utput data should be filled into iicrwd before setting fu_en[7:6] as 01. fu_en[7:6] will be auto - clear by hardware, so setting fu_en[7:6] repeatedly is necessary.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 73 - 15. spi function - serial peripheral interface serial peripheral interface (spi) is a synchron ous protocol that allows a master device to initiate communication with slave devices. the interrupt vector is 4bh. there are 4 signals used in spi, they are spi_mosi: data output in the master mode, data input in the slave mode, spi_miso: data input in the master mode, data output in the slave mode , spi_sck: clock output from the master, the above data are synchronous to this signal . spi_ss: input in the slave mode. this slave device detects this signal to judge if it is selected by the master. as show n i n fig. 15 - 1 in the master mode, it can select the desired slave device by any io with value = 0. a s below figure is an example showing the relation of the 4 signals between master and slaves. fig. 15 - 1 : spi signals between master and slave devices there is only one channel spi interface. the spi sfrs are shown as below: mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst spi function spic1 sp i control register 1 f1h spien spims s spiss p spick p spick e spibr[2:0] 08h spic2 spi control register 2 f2h spifd tbc[2:0] spirs t rbc[2:0] 00h spis spi status register f5h spirf spiml s spiov spitxi f spitd r spirxi f spird r spirs 40h spitxd spi transmit data buffer f3h spitxd[7:0] 00h spirxd spi receive data buffer f4h spirxd[7:0] 00h master mosi miso clk io io sla ve 1 mosi miso clk ss slave 2 mosi miso clk ss
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 74 - mnemonic:spic1 address:f1h 7 6 5 4 3 2 1 0 reset spien spimss spissp spickp spicke spibr[2:0] 08h spien: enable spi module. spien = 1 - is enable. spien = 0 - is disable. spimss: master or slave mode select spimss = 1 - is master mode. spimss = 0 - is slave mode. spissp: ss or cs active polarity.(slave mode used only) spissp = 1 - high active. spissp = 0 - low active. spickp: clock idle polarity select. spickp = 1 - sck will idle high. ex : spickp = 0 - sck will idle low. ex : spicke: clock sample edge select. spicke = 1 - rising edge latch data. spicke = 0 - falling edge latch data. * to ensure the data latch stability, sm39 r16a6 generate the output data as shown in the following example, the other side can latch the stable data no matter in rising or falling edge. sufficient set - up time sufficient hold time
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 75 - spibr[2:0]: spi baud rate select. (master mode used only) spibr[2:0] baud rate 0:0:0 fosc/4 0:0:1 fosc /8 0:1:0 fosc /16 0:1:1 f osc /32 1:0:0 fosc /64 1:0:1 fosc /128 1:1:0 fosc /256 1:1:1 fosc /512 mnemonic: spic2 address: f2h 7 6 5 4 3 2 1 0 reset spifd tbc[2:0] spirst rbc[2:0] 00h spifd: full - duplex mode enable. spifd = 1 is enable full - duplex mode. spifd = 0 is di sable full - duplex mode. when it is set, the tbc[2:0] and rbc[2:0] will be reset and keep to zero. when the master device transmit s data to the slave device via the mosi line, the slave device responds by sending data to the master device via the miso line . this implies full - duplex transmission with both data out and data in synchronized with the same clock. a s shown in fig 15 - 2. input shift register spirxd output shift register spitxd clock generator output shift register spitxd syncmos master input shift register spirxd syncmos slave miso mosi sck miso mosi sck fig. 15 - 2 : spi mater and slave transfer method
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 76 - spirst: spi re - start (slave mode used only) spirst = 0 - re - start function disable.spi transmit /receive data when ss active. in spitxd/spirxd buffer, data got from previous ss active period will not be removed (i.e. it's valid). spirst = 1 - re - start funct ion enable.spi transmit /receive new data when ss re - active; in spitxd/spirxd buffer, data got from previous ss active period will be removed (i.e. it's invalid). t bc[2:0]: spi transmit ter bit counter. t bc[2:0] bit counter 0:0:0 8 bits output 0:0:1 1 bit output 0:1:0 2 bits output 0:1:1 3 bits output 1:0:0 4 bits output 1:0:1 5 bits output 1:1:0 6 bits output 1:1:1 7 bits output rbc[2:0]: spi receiver bit counter. rbc[2:0] bit counter 0:0:0 8 bits input 0:0:1 1 bit input 0:1:0 2 bits input 0:1 :1 3 bits input 1:0:0 4 bits input 1:0:1 5 bits input 1:1:0 6 bits input 1:1:1 7 bits input mnemonic: spis address:f5h 7 6 5 4 3 2 1 0 reset spirf spimls spiov spitxif spitdr spirxif spirdr spirs 40h spirf: spi ss pin release flag. this bit i s set when ss pin release & spirst as ?1?. spimls: msb or lsb first output /input select. spimls = 1 is msb first output/input. spimls = 0 is lsb first output/input. spiov: overflow flag. when spirdr is set and next data already into shift register, this flag will be set. it is clear by hardware, when spirdr is cleared. spitxif: transmit interrupt flag. this bit is set when the data of the spitxd register is downloaded to the shift register. spitdr: transmit data ready. when mcu finish writing data to s pitxd register, the mcu needs to set this bit to ?1? to inform the spi module to send the data. after spi module finishes sending the data from spitxd, this bit will be cleared automatically. spirxif: receive interrupt flag.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 77 - this bit is set after the spir xd is loaded with a newly receive data. spirdr: receive data ready. the mcu must clear this bit after it gets the data from spirxd register. the spi module is able to write new data into spirxd only when this bit is cleared. spirs: receive start. this bi t set to ?1? to inform the spi module to receive the data into spirxd register. mnemonic: spitxd address: f3h 7 6 5 4 3 2 1 0 reset spitxd[7:0] 00h spitxd[7:0]: transmit data buffer. mnemonic: spirxd address: f4h 7 6 5 4 3 2 1 0 reset spirxd[7: 0] 00h spirxd[7:0]: receive data buffer. p.s. miso pin must be float when ss or cs no - active in slave mode.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 78 - 16. lvi & lvr ? low voltage interrupt and low voltage reset the interrupt vector 63h mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst watchdog timer rsts reset status register a1h - lvrlp intf lvrlp f pdrf wdtf swrf lvrf porf 00h lvc low voltage control register e6h lvi_e n lvrlpe lvre lv if lvrlp inte - lvis[1:0] 20h mnemonic: rsts address: a1h 7 6 5 4 3 2 1 0 rese t - lvrlp intf lvrlpf pdrf wdtf swrf lvrf porf 00h lvrlpintf : ? internal ? low voltage reset flag. when mcu is reset by lvr_lp_int , lvrlpintf flag will be set to one by hardware. this flag clear by software . lvrlpf : ? external ? low voltage reset flag. whe n mcu is reset by lvr(external low power ) , lvrlpf flag will be set to one by hardware. this flag clear by software . pdrf: pad reset flag. when mcu is reset by reset pad , pdr f flag will be set to one by hardware. this flag clear by software. lvrf: low vol tage reset flag. when mcu is reset by lvr , lvrf flag will be set to one by hardware. this flag clear by software . porf: power on reset flag. when mcu is reset by por , porf flag will be set to one by hardware. this flag clear by software . mnemonic: lvc a ddress: e6h 7 6 5 4 3 2 1 0 reset lvi_en lvr lpe lvre lvif lvrlp inte - lvis [1:0] 20h lvi_en: low voltage interrupt function enable bit. lvi_en = 0 - disable low voltage detect function. lvi_en = 1 - enable low voltage detect function. lvrlpe : extern al low voltage reset function (low power) enable bit. lvr lp e = 0 - enable external low voltage reset (low power) function. lvr lp e = 1 - disable external low voltage reset (low power) function. lvre: external low voltage reset function enable bit. lvrxe = 0 - disable external low voltage reset function.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 79 - lvrxe = 1 - enable external low voltage reset function. note: lvr = 1. 50 v lvif: low voltage interrupt flag (i.e., low v oltage interrupt status flag) lvrlpinte: lvr_lp_int( ? in ternal? low voltage reset ) funct ion enable bit. lvr lpint e = 0 - disable in ternal low voltage reset function. lvr lpint e = 1 - enable in ternal low voltage reset function. lvis [1:0] : lvi level select: 00: 1.65v 01: 2.60v 10: 3.20v 11: 4.00v
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 80 - 17. 10- bit analog - to - digital converter (adc) the SM39R16A6 provides 8 channels 10 - bit adc. the digital output data [ 9:0] were put into adcd [9:0]. the adc the block diagram show in fig. 17 - 1 the adc interrupt vector is 53h. mux high speed 10 bits adc module adcc 1 [ 7 : 0 ] avss avdd adc 0 adc 7 ? adc 6 adc clock divider ? adcch [ 2 : 0 ] adccs [ 4 : 0 ] fosc start vdd vss ? ? adcd [ 9 : 0 ] adc _ isr fig. 17 - 1 : adc analog to digital converter operation set the adc sfr show as below: mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst adc adcc1 adc control register 1 abh adc7 en adc6 en adc5 en adc4 en ad c3 en adc2 en adc1 en adc0 en 00h adcc2 adc control register 2 ach start adju st - ext trigger en adcm ode adcch[2:0] 0 8 h adcdh adc data high byte adh adcdh [7:0] 00h adcdl adc data low byte aeh adcdl [7:0] 00h adccs adc clock select afh - - - adccs[4:0] 00h mnemonic: adcc1 address: abh 7 6 5 4 3 2 1 0 reset adc7en adc6en adc5en adc4en adc3en adc2en adc1en adc0en 00h adc7en: adc channels 7 enable. adc7en = 1 - enable adc channel 7 adc6en: adc channels 6 enable.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 81 - adc6en = 1 - enable adc channel 6 adc 5en: adc channels 5 enable. adc5en = 1 - enable adc channel 5 adc4en: adc channels 4 enable. adc4en = 1 - enable adc channel 4 adc3en: adc channels 3 enable. adc3en = 1 - enable adc channel 3 adc2en: adc channels 2 enable. adc2en = 1 - enable adc channe l 2 adc1en: adc channels 1 enable. adc1en = 1 - enable adc channel 1 adc0en: adc channels 0 enable. adc0en = 1 - enable adc channel 0 mnemonic: adcc2 address: ach 7 6 5 4 3 2 1 0 reset start adjust - exttrigg eren adcmo de adcch[2:0] 0 8 h star t : wh en this bit is set, the adc will be start conversion. (sw trigger conversion) adjust : adjust the format of adc conversion data. adjust = 0 - (default value) adc data high byte adcd [9:2] = adcdh [7:0]. adc data low byte adcd [1:0] = adcdl [1:0]. adjust = 1 - adc data high byte adcd [9:8] = adcdh [1:0]. adc data low byte adcd [7:0] = adcdl [7:0]. exttriggeren : external pin trigger adc to start conversion. (hw external trigger conversion) 0 = disable . 1 = enable . adcmod e : 0 = continuous mode . 1 = sin gle - shot mode .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 82 - adcch[2:0] adc channel select. adcch [2:0] channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 adjust = 0: mnemonic: adcdh address: adh 7 6 5 4 3 2 1 0 reset adcd[9] adcd[8] adcd[7] adcd[6] adcd[5] adcd[4] adcd[3] adc d[2] 00h mnemonic: adcdl address: aeh 7 6 5 4 3 2 1 0 reset - - - - - - adcd[1] adcd[0] 00h adjust = 1: mnemonic: adcdh address: adh 7 6 5 4 3 2 1 0 reset - - - - - - adcd[9] adcd[8] 00h mnemonic: adcdl address: aeh 7 6 5 4 3 2 1 0 reset adcd[ 7] adcd[6] adcd[5] adcd[4] adcd[3] adcd[2] adcd[1] adcd[0] 00h adcd[9:0]: adc data register. mnemonic: adccs address: afh 7 6 5 4 3 2 1 0 reset - - - adccs[4] adccs[3] adccs[2] adccs[1] adccs[0] 00h adccs[4:0]: adc clock select. *the adc clock max imum 12.5mhz. *the adc conversion rate maximum 961 khz. adccs[4:0] adc clock(hz) clocks for adc conversion 00000 fosc /2 26 00001 fosc /4 52 00010 fosc /6 78 00011 fosc /8 104 00100 fosc /10 130 00101 fosc /12 156 00110 fosc /14 182 00111 fosc /16 208 01000 fosc /18 234 01001 fosc /20 260
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 83 - 01010 fosc /22 286 01011 fosc /24 312 01100 fosc /26 338 01101 fosc /28 364 01110 fosc /30 390 01111 fosc /32 416 10000 fosc /34 442 10001 fosc /36 468 10010 fosc /38 494 10011 fosc /40 520 10100 fosc /42 546 10101 fosc /44 572 10110 fosc /46 598 10111 fosc /48 624 11000 fosc /50 650 11001 fosc /52 676 11010 fosc /54 702 11011 fosc /56 728 11100 fosc /58 754 11101 fosc /60 780 11110 fosc /62 806 11111 fosc /64 832 ) 1 ( 2 fosc _ + = adccs clock adc 13 adc_clock _ _ = rate conversion adc
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 84 - 18. in - system programming (internal isp) the SM39R16A6 can generate flash control signal by internal hardware circuit. users utilize flash control register, flash address register and flash data register to perform the isp function wi thout removing the SM39R16A6 from the system. the SM39R16A6 provides internal flash control signals which can do flash program/chip erase/page erase/protect functions. user need to design and use any kind of interface which SM39R16A6 can input data. user t hen utilize isp service program to perform the flash program/chip erase/page erase/protect functions. 18.1 isp service program the isp service program is a user developed firmware program which resides in the isp service program space. after user developed the isp service program, user then determine the size of the isp service program. user need to program the isp service program in the SM39R16A6 for the isp purpose. the isp service programs were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between SM39R16A6 and host device which output data to the SM39R16A6 . for example, if user utilize uart interface to receive/ transmit data between SM39R16A6 and host device, the isp service program should include baud rate, checksum or parity check or any error - checking mechanism to avoid data tra nsmission er ror. the isp service program can be initiated under SM39R16A6 active or idle mode. it can not be initiated under power down mode. 18.2 lock bit (n) the lock bit n has two functions: one is for service program size configuration and the other is to lock the isp service program space from flash erase function. the isp service program space address range $3c00 to $3fff. it can be divided as blocks of n*128 byte. (n=0 to 8). when n=0 means no isp function, all of 16 k byte flash memory can be used as program memory. when n=1 means isp service program occupies 128 byte while the rest of 15.875k byte flash memory can be used as program memory. the maximum isp service program allowed is 1k byte when n= 8 . under such configuration, the usable program memory space is 15k byte. after n determined, SM39R16A6 will reserve the isp service program space downward from the top of the program addre ss $3fff. the start address of the isp service program located at $3x00 while x is depending on the lock bit n. please see section 3.1 program memory diagram for this isp service program space structure. the lock bit n function is different from the flash protect function. the flash erase function can erase all of the flash memory except for the locked isp service program space. if the flash not has been protected, the content of isp service program still can be read. if the flash has been protected, the ov erall content of flash program memory space including isp service program space can not be read. as given in table 18- 1 .
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 85 - table 18- 1 isp code area isp service program address 0 no isp service program 1 128 bytes ($3f80h ~ $3fffh) 2 256 bytes ($3f00h ~ $3fffh) 3 384 bytes ($3e80h ~ $3fffh) 4 512 bytes ($3e00h ~ $3fffh) 5 640 bytes ($3d80h ~ $3fffh) 6 768 bytes ($3d00h ~ $3fffh) 7 896 bytes ($3c80h ~ $3fffh) 8 1.0 k bytes ($3c 00h ~ $3fffh) isp service program configurable in n* 128 byte (n= 0 ~ 8) 18.3 program the isp service program after lock bit n is set and isp service program been programmed, the isp service program memory will be protected (locked) automatically. the lock bit n has its own program/erase timing. it is different from the flash memory program/erase timing so the locked isp service program can not be erased by flash erase function. if user needs to erase the locked isp service program, he can do it by writer only. user can not change isp service program when SM39R16A6 was in system. 18.4 initiate isp service program to initiate the isp service program is to load the program counter (pc) with start address of isp service program and execute it. there are four ways to do so: (1) blank reset. hardware reset with first flash address blank ($0000=#ffh) will load the pc with start address of isp service program. the hardware reset includes max810 (power on reset) and external pad reset. the hardware will issue a strobe window abo ut 256us after hardware reset. (2) execute jump instruction can load the start address of the isp service program to pc. (3) enter?s isp service program by hardware setting. user can force SM39R16A6 enter isp service program by setting p1.2, p1.3 ?active low? or p1.4 ? active low? during hardware reset period. the hardware reset includes max810 (power on reset) and external pad reset. the hardware will issue after hardware reset. in application system design, user should take care of the setting of p1. 2,p1.3 or p 1.4 at reset period to prevent SM39R16A6 from entering isp service program. (4) enter?s isp service program by hardware setting, the p 3 . 0 (rxd) will be detected the two clock signals during hardware reset period. the hardware reset includes max810 (power on r eset) and external pad reset. the hardware will issue to detect 2 clock signals after hardware reset. during the strobe window, the hardware will detect the status of p1 .2, p1.3 (or p1.4) /p1. 0 . if they meet one of above conditions, chip will switch to isp mode automatically. after isp service program executed, user need to reset the SM39R16A6 , either by hardware reset or by wdt, or jump to the address $0000 to re - start the firmware program.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 86 - there are 6 kinds of entry mechanisms for user different applicati ons. this entry method will select on the writer or isp. (1) first address blank. i.e. $0000 = 0xff. and triggered by internal reset signal. ( entry mechanism 1 ) (2) first address blank. i.e. $0000 = 0xff. and triggered by pad reset signal. ( entry mechanism 1 ) (3) p1. 2 = 0 & p1.3 = 0. and triggered by internal reset signal. ( entry mechanism 2 ) (4) p1. 2 = 0 & p1.3 = 0. and triggered by pad reset signal. ( entry mechanism 2 ) (5) p1.4 = 0. and triggered by internal reset signal. ( entry mechanism 3 ) (6) p1.4 = 0. and triggere d by pad reset signal. ( entry mechanism 3 ) (7) p 3 . 0 input 2 clocks. and triggered by internal reset signal. ( entry mechanism 4 ) (8) p 3 . 0 input 2 clocks. and triggered by pad reset signal. ( entry mechanism 4 ) 18.5 isp register ? takey, ifcon, ispfah, ispfal, ispfd and ispfc mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst isp function takey time access key register f7h takey [7:0] 00h ifcon interface control register 8fh - cdpr - - - - - ispe 00h ispfah isp flash address ? high register e1h ispfah [7:0] ffh ispfal isp flash address - low register e2h ispfal [7:0] ffh ispfd isp flash data register e3h ispfd [7:0] ffh ispfc isp flash control register e4h emf1 emf2 emf3 emf4 - ispf.2 ispf.1 ispf.0 00h mnemonic: takey addre ss: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h isp enable bit (ispe) is read - only by default, software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the ispe bit write attribute. that is: mov takey, #55h m ov takey, #0aah mov takey, #5ah mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset - cdpr - - - - - ispe 00h the bit 0 (ispe) of ifcon is isp enable bit. user can enable overall SM39R16A6 isp function by setting ispe bit to 1, to disable overall isp f unction by set ispe to 0. the function of ispe behaves like a security key. user can disable overall isp function to prevent software program be erased accidentally. isp registers ispfah, ispfal, ispfd and ispfc are read - only by default. software must be s et ispe bit to 1 to enable these 4 registers write attribute.
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 87 - mnemonic: ispfah address: e1h 7 6 5 4 3 2 1 0 reset ispfah 7 ispfah 6 ispfah5 ispfah4 ispfah3 ispfah2 ispfah1 ispfah0 ffh ispfah [ 7 :0]: flash address - high for isp function mnemonic: ispfal address: e2h 7 6 5 4 3 2 1 0 reset ispfal7 ispfal6 ispfal5 ispfal4 ispfal3 ispfal2 ispfal1 ispfal0 ffh ispfal [7:0]: flash address - low for isp function the ispfah & ispfal provide the 1 6 - bit flash memory address for isp function. the flash memory ad dress should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the isp service program space address, the flash program/page erase of isp function executed thereafter will hav e no effect. mnemonic: ispfd address: e3h 7 6 5 4 3 2 1 0 reset ispfd7 ispfd6 ispfd5 ispfd4 ispfd3 ispfd2 ispfd1 ispfd0 ffh ispfd [7:0]: flash data for isp function. the ispfd provide the 8 - bit data register for isp function. mnemonic: ispfc addres s: e4h 7 6 5 4 3 2 1 0 reset emf1 emf 2 emf3 emf4 - ispf[2] ispf[1] ispf[0] 00h emf1: entry mechanism (1) flag, clear by reset. (read only) emf 2 : entry mechanism ( 2 ) flag, clear by reset. (read only) emf3: entry mechanism (3) flag, clear by reset. (re ad only) emf4: entry mechanism (4) flag, clear by reset. (read only) ispf [2:0]: isp function select bit. ispf[2:0] isp function 000 byte program 001 chip protect 010 page erase 011 chip erase 100 write option 101 read option 110 erase option 1 11 reserved one page of flash memory is 128byte the option function can access the xtal1 and xtal2 swap to i/o pins select(description i n section 1.2) internal reset time select(description in section
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 88 - 1.4.1) clock source select(description in section 1.5) reset swap to i/o pins function select(description in section 5) wdten control bit(description in section 10) or isp entry mechanisms se lect(description in section 18). when chip protected or no isp service, option can only read. the choice isp function will start to execute once the software write data to ispfc register. to perform byte program/page erases isp function, user need to sp ecify flash address at first. when performing page erase function, SM39R16A6 will erase entire page which flash address indicated by ispfah & ispfal registers located within the page. e.g. flash address: $ xy 00 page erase function will erase from $xy00 to $xy 7 f to perform the chip erase isp function, SM39R16A6 will erase all the flash program memory except the isp service program space. to perform chip protect isp function, the SM39R16A6 flash memory content will be read #00h. e.g. isp service program to d o the byte program - to program #22h to the address $1005h mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable ispe write attribute orl ifcon, #01h ; enable sm39r 16a 6 isp function mov ispfah, #10h ; set flash address - high, 10h mov ispf al, #05h ; set flash address - low, 05h mov ispfd, #22h ; set flash data to be programmed, data = 22h mov ispfc, #00h ; start to program #22h to the flash address $1005h mov takey, #55h mov takey, #0aah mov takey, #5ah ; enable ispe write attribute anl ifcon, #0feh ; disable SM39R16A6 isp function
sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 89 - operating conditions symbol description min. typ. max. unit. remarks ta operating temperature - 40 25 85 ambient temperature under bias vdd supply voltage 1.8 5.5 v vref internal reference voltage 1.1 1.2 1. 3 v dc characteristics ta = - 40 to 85 , vcc = 5.0v symbol parameter valid min typical max units conditions vil1 input low - voltage port 0,1, 2,3 - 0.5 - 0.8 v vcc=5v vil2 input low - voltage res, xtal1 0 - 0.8 v - vih1 input high - voltage port 0,1,2,3 2.0 - vcc + 0.5 v - vih2 input high - voltage res, xtal1 70%vcc - vcc + 0.5 v - vol output low - voltage port 0 (3.) - - 0.4 5 v iol= 40 ma vcc=5v port 1,2,3 (4.) - - 0.4 5 v iol= 20 ma vcc=5v voh1 output high - voltage using strong pull - up(1) port 0 4.6 - - v ioh= - 12ma port 1,2,3 4.6 - - v ioh= - 7 ma voh2 output high - voltage using weak pull - up(2) port 0 , 1,2,3 2. 6 - - v ioh= - 350 ua iil logic 0 input current port 0,1,2,3 - - - 75 ua vin= 0.45v itl logical transition current port 0,1,2,3 - - - 650 ua vin= 2.0v ili input leakage current port 0,1,2,3 - - 10 ua 0.45v sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 90 - ta = - 40 to 85 , vcc = 3.0v symbol parameter valid min typical max units conditions vil1 input low - voltage port 0,1 ,2,3 - 0.5 - 0.8 v vcc=3.0v vil2 input low - voltage res, xtal1 0 - 0.8 v - vih1 input high - voltage port 0,1,2,3 2.0 - vcc + 0.5 v - vih2 input high - voltage res, xtal1 70%vcc - vcc + 0.5 v - vol output low - voltage port 0 (3.) - - 0.45 v iol=20ma vcc=3v port 1,2,3 (4.) - - 0.45 v iol=12ma vcc=3v voh1 output high - voltage using strong pull - up(1) port 0 2.6 - - v ioh= - 9ma port 1,2,3 2.6 - - v ioh= - 5ma voh2 output high - voltage using weak pull - up(2) port 0,1,2,3 2.4 - - v ioh= - 70ua iil logic 0 input current port 0,1,2,3 - - - 75 ua vin= 0.45v itl logical transitio n current port 0,1,2,3 - - - 650 ua vin=1.5v ili input leakage current port 0,1,2,3 - - 10 ua 0.45v sm 39 r16a6 8 - bit micro - controller 16 kb with isp flash & 1k+256 b ram embedded specifications subject to change without notice contact your sales representatives f or the most recent information . i ssfd - m 079 ver d SM39R16A6 0 6 / 30 /201 5 - 91 - lvi& lvr characteristics lvr min typical max 1.8v ~ 5.5v vil=1.42v (vih=1.62v) vil=1.50v (vih=1.70v) vil=1.57v (vih=1.77v) lvi min typical max lvis[1:0] = 00 vil=1.57v (vih=1.77v) vil=1.65v (vih=1.85v) vil=1.73v (vih=1.93v) lvis[1:0] = 01 vil=2.47v (vih=2.67v) vil=2.60v (vih=2.80v) vil=2.73v (vih=2.93v) lvis[1:0] = 10 vil=3.04v (vih=3.24v) vil=3.20v (vih=3.40v) vil=3.36v (vih=3.56v) lvis[1:0] = 11 vil=3.80v (vih=4.00v) vil=4.00v (vih=4.20v) vil=4.20v (vih=4.40v)

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